UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 152 of 368
NXP Semiconductors
UM10375
Chapter 10: LPC13xx USB device controller
10.10.3.5.1 Data transfer
When the software wants to read the data from an endpoint buffer it should make the
Read Enable bit high and should program the logical endpoint number. The control logic
will first fetch the packet length to the receive packet length register. Also the hardware
fills the receive data register with the first word of the packet.
The software can now start reading the receive data register. When the end of packet is
reached the Read Enable bit will be disabled by the control logic and RxENDPKT bit is set
in the Device interrupt status register.
If the software makes the Read Enable bit low midway, the reading will be terminated. In
this case the data will remain in the RAM. When the Read Enable signal is made high
again for this endpoint, data will be read from the beginning.
For writing data to an endpoint buffer, the Write Enable bit should be made high and
software should write to the Tx Packet Length register the number of bytes it is going to
send in the packet. It can then write data continuously in the Transmit Data register. When
the control logic receives the number of bytes programmed in the Tx Packet length
register, it will reset the Write Enable bit. If the software resets this bit midway, writing will
start again from the beginning.
Both Read Enable and Write Enable bits can be high at the same time for the same logical
endpoint. The interleaved read and write operation is possible.
Remark: It takes 3 clock cycle to fetch the packet length from the RAM after programming
the USB control register. There can be a corruption on the packet length value read if the
reading of the packet length occurs immediately (in the very next clock cycle) after the
programming of USB control register. To avoid this problem, a NOP instruction has to be
inserted in between the programming of USBCtrl registers and reading of packet length
registers.
Table 173. USB Control register (USBCtrl - address 0x4002 0028) bit description
Bit Symbol Value Description Reset
value
0 RD_EN Read mode control. Enables reading data from the OUT
endpoint buffer for the endpoint specified in the
LOG_ENDPOINT field using the USBRxData register.
This bit is cleared by hardware when the last word of
the current packet is read from USBRxData.
0
0 Read mode is disabled.
1 Read mode is enabled.
1 WR_EN Write mode control. Enables writing data to the IN
endpoint buffer for the endpoint specified in the
LOG_ENDPOINT field using the USBTxData register.
This bit is cleared by hardware when the number of
bytes in USBTxLen have been sent.
0
0 Write mode is disabled.
1 Write mode is enabled.
5:2 LOG_ENDPOINT - Logical Endpoint number. 0x0
31:6 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
NA
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