NXP Semiconductors LPC1311 User Manual

UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 25 of 368
NXP Semiconductors
UM10375
Chapter 3: LPC13xx System configuration
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
3.5.17 System AHB clock divider register
This register divides the main clock to provide the system clock to the core, memories,
and the peripherals. The system clock can be shut down completely by setting the DIV
bits to 0x0.
3.5.18 System AHB clock control register
The SYSAHBCLKCTRL register enables the clocks to individual system and peripheral
blocks. The system clock (sys_ahb_clk[0], bit 0 in the SYSAHBCLKCTRL register)
provides the clock for the AHB to APB bridge, the AHB matrix, the ARM Cortex-M3, the
Syscon block, and the PMU. This clock cannot be disabled.
Table 23. Main clock source update enable register (MAINCLKUEN, address 0x4004 8074)
bit description
Bit Symbol Value Description Reset value
0 ENA Enable main clock source update 0x0
0 No change
1 Update clock source
31:1 - - Reserved 0x00
Table 24. System AHB clock divider register (SYSAHBCLKDIV, address 0x4004 8078) bit
description
Bit Symbol Description Reset value
7:0 DIV System AHB clock divider values
0: System clock disabled.
1: Divide by 1.
to
255: Divide by 255.
0x01
31:8 - Reserved 0x00
Table 25. System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit
description
Bit Symbol Value Description Reset
value
0 SYS Enables clock for AHB to APB bridge, to the AHB
matrix, to the Cortex-M3 FCLK and HCLK, to the
SysCon, and to the PMU. This bit is read only.
1
0 Reserved
1 Enabled
1 ROM Enables clock for ROM. 1
0 Disabled
1 Enabled
2 RAM Enables clock for RAM. 1
0 Disabled
1 Enabled

NXP Semiconductors LPC1311 Specifications

General

Brand	NXP Semiconductors
Model	LPC1311
Category	Controller
Language	English