UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 359 of 368
NXP Semiconductors
UM10375
Chapter 23: LPC13xx Supplementary information
23.4 Figures
Fig 1. LPC13xx block diagram. . . . . . . . . . . . . . . . . . . . .7
Fig 2. LPC13xx memory map . . . . . . . . . . . . . . . . . . . . .9
Fig 3. LPC13xx CGU block diagram . . . . . . . . . . . . . . .14
Fig 4. Start-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Fig 5. System and USB PLL block diagram. . . . . . . . . .48
Fig 6. Power profiles pointer structure. . . . . . . . . . . . . .54
Fig 7. LPC1311/01 and LPC1313/01 clock configuration
for power API use . . . . . . . . . . . . . . . . . . . . . . . .55
Fig 8. Power profiles usage . . . . . . . . . . . . . . . . . . . . . .59
Fig 9. Standard I/O pin configuration . . . . . . . . . . . . . . .86
Fig 10. LPC1342/43 LQFP48 package . . . . . . . . . . . . .119
Fig 11. LPC1342/43 HVQFN33 package. . . . . . . . . . . .120
Fig 12. LPC1313 LQFP48 package. . . . . . . . . . . . . . . .121
Fig 13. LPC1311/13 HVQFN33 package. . . . . . . . . . . .122
Fig 14. Masked write operation to the GPIODATA
register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Fig 15. Masked read operation . . . . . . . . . . . . . . . . . . .135
Fig 16. USB device controller block diagram . . . . . . . .138
Fig 17. USB SoftConnect interfacing . . . . . . . . . . . . . . .139
Fig 18. USB clocking . . . . . . . . . . . . . . . . . . . . . . . . . . .142
Fig 19. USB device driver pointer structure. . . . . . . . . .170
Fig 20. Auto-RTS Functional Timing . . . . . . . . . . . . . . .191
Fig 21. Auto-CTS Functional Timing . . . . . . . . . . . . . . .192
Fig 22. Auto-baud a) mode 0 and b) mode 1 waveform 197
Fig 23. Algorithm for setting UART dividers. . . . . . . . . .200
Fig 24. UART block diagram . . . . . . . . . . . . . . . . . . . . .206
Fig 25. I
2
C-bus configuration . . . . . . . . . . . . . . . . . . . . .208
Fig 26. Format in the Master Transmitter mode. . . . . . .218
Fig 27. Format of Master Receiver mode . . . . . . . . . . .219
Fig 28. A Master Receiver switches to Master Transmitter
after sending Repeated START. . . . . . . . . . . . .219
Fig 29. Format of Slave Receiver mode . . . . . . . . . . . .220
Fig 30. Format of Slave Transmitter mode . . . . . . . . . .220
Fig 31. I
2
C serial interface block diagram . . . . . . . . . . .221
Fig 32. Arbitration procedure . . . . . . . . . . . . . . . . . . . . .223
Fig 33. Serial clock synchronization. . . . . . . . . . . . . . . .223
Fig 34. Format and states in the Master Transmitter
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
Fig 35. Format and states in the Master Receiver
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
Fig 36. Format and states in the Slave Receiver mode.235
Fig 37. Format and states in the Slave Transmitter
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
Fig 38. Simultaneous Repeated START conditions from two
masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
Fig 39. Forced access to a busy I
2
C-bus . . . . . . . . . . .240
Fig 40. Recovering from a bus obstruction caused by a
LOW level on SDA. . . . . . . . . . . . . . . . . . . . . . .241
Fig 41. Texas Instruments Synchronous Serial Frame
Format: a) Single and b) Continuous/back-to-back
Two Frames Transfer. . . . . . . . . . . . . . . . . . . . .259
Fig 42. SPI frame format with CPOL=0 and CPHA=0 (a)
Single and b) Continuous Transfer). . . . . . . . . .260
Fig 43. SPI frame format with CPOL=0 and CPHA=1 . .261
Fig 44. SPI frame format with CPOL = 1 and CPHA = 0 (a)
Single and b) Continuous Transfer). . . . . . . . . .262
Fig 45. SPI Frame Format with CPOL = 1 and
CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Fig 46. Microwire frame format (single transfer) . . . . . . 264
Fig 47. Microwire frame format (continuous transfers) . 264
Fig 48. Microwire frame format setup and hold details . 265
Fig 49. Sample PWM waveforms with a PWM cycle length
of 100 (selected by MR3) and MAT3:0 enabled as
PWM outputs by the PWCON register. . . . . . . . 278
Fig 50. A timer cycle in which PR=2, MRx=6, and both
interrupt and reset on match are enabled . . . . . 278
Fig 51. A timer cycle in which PR=2, MRx=6, and both
interrupt and stop on match are enabled . . . . . 278
Fig 52. 16-bit counter/timer block diagram . . . . . . . . . . 279
Fig 53. Sample PWM waveforms with a PWM cycle length
of 100 (selected by MR3) and MAT3:0 enabled as
PWM outputs by the PWCON register. . . . . . . . 292
Fig 54. A timer cycle in which PR=2, MRx=6, and both
interrupt and reset on match are enabled . . . . . 292
Fig 55. A timer cycle in which PR=2, MRx=6, and both
interrupt and stop on match are enabled . . . . . 292
Fig 56. 32-bit counter/timer block diagram . . . . . . . . . . 293
Fig 57. System tick timer block diagram . . . . . . . . . . . . 295
Fig 58. Watchdog block diagram. . . . . . . . . . . . . . . . . . 303
Fig 59. Watchdog Timer block diagram. . . . . . . . . . . . . 306
Fig 60. Early Watchdog Feed with Windowed Mode
Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Fig 61. Correct Watchdog Feed with Windowed Mode
Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Fig 62. Watchdog Warning Interrupt . . . . . . . . . . . . . . . 311
Fig 63. Boot process flowchart . . . . . . . . . . . . . . . . . . . 324
Fig 64. IAP parameter passing . . . . . . . . . . . . . . . . . . . 337
Fig 65. Algorithm for generating a 128 bit signature . . . 346
Fig 66. Connecting the SWD pins to a standard SWD
connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
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