NXP Semiconductors LPC1311 User Manual

UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 182 of 368
NXP Semiconductors
UM10375
Chapter 12: LPC13xx UART
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Table 193. Register overview: UART (base address: 0x4000 8000)
Name Access Address
offset
Description Reset
value
[1]
U0RBR RO 0x000 Receiver Buffer Register. Contains the next received character to be read.
When DLAB=0.
NA
U0THR WO 0x000 Transmit Holding Register. The next character to be transmitted is written
here. When DLAB=0.
NA
U0DLL R/W 0x000 Divisor Latch LSB. Least significant byte of the baud rate divisor value. The
full divisor is used to generate a baud rate from the fractional rate divider.
When DLAB=1.
0x01
U0DLM R/W 0x004 Divisor Latch MSB. Most significant byte of the baud rate divisor value. The
full divisor is used to generate a baud rate from the fractional rate divider.
When DLAB=1.
0x00
U0IER R/W 0x004 Interrupt Enable Register. Contains individual interrupt enable bits for the 7
potential UART interrupts. When DLAB=0.
0x00
U0IIR RO 0x008 Interrupt ID Register. Identifies which interrupt(s) are pending. 0x01
U0FCR WO 0x008 FIFO Control Register. Controls UART FIFO usage and modes. 0x00
U0LCR R/W 0x00C Line Control Register. Contains controls for frame formatting and break
generation.
0x00
U0MCR R/W 0x010 Modem control register 0x00
U0LSR RO 0x014 Line Status Register. Contains flags for transmit and receive status,
including line errors.
0x60
U0MSR RO 0x018 Modem status register 0x00
U0SCR R/W 0x01C Scratch Pad Register. Eight-bit temporary storage for software. 0x00
U0ACR R/W 0x020 Auto-baud Control Register. Contains controls for the auto-baud feature. 0x00
- - 0x024 Reserved -
U0FDR R/W 0x028 Fractional Divider Register. Generates a clock input for the baud rate
divider.
0x10
- - 0x02C Reserved -
U0TER R/W 0x030 Transmit Enable Register. Turns off UART transmitter for use with software
flow control.
0x80
- - 0x034 -
0x048
Reserved -
U0RS485CTRL R/W 0x04C RS-485/EIA-485 Control. Contains controls to configure various aspects of
RS-485/EIA-485 modes.
0x00
U0RS485ADR
MATCH
R/W 0x050 RS-485/EIA-485 address match. Contains the address match value for
RS-485/EIA-485 mode.
0x00
U0RS485DLY R/W 0x054 RS-485/EIA-485 direction control delay. 0x00

NXP Semiconductors LPC1311 Specifications

General

Brand	NXP Semiconductors
Model	LPC1311
Category	Controller
Language	English