NXP Semiconductors LPC1311 User Manual

UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 354 of 368
NXP Semiconductors
UM10375
Chapter 23: LPC13xx Supplementary information
address 0x4004 4038) bit description . . . . . . .97
Table 110. IOCON_PIO3_4 register (IOCON_PIO3_4,
address 0x4004 403C) bit description . . . . . . .98
Table 111. IOCON_PIO2_4 register (IOCON_PIO2_4,
address 0x4004 4040) bit description . . . . . . .98
Table 112. IOCON_PIO2_5 register (IOCON_PIO2_5,
address 0x4004 4044) bit description . . . . . . .99
Table 113. IOCON_PIO3_5 register (IOCON_PIO3_5,
address 0x4004 4048) bit description . . . . . . .99
Table 114. IOCON_PIO0_6 register (IOCON_PIO0_6,
address 0x4004 404C) bit description . . . . . .100
Table 115. IOCON_PIO0_7 register (IOCON_PIO0_7,
address 0x4004 4050) bit description. . . . . . .100
Table 116. IOCON_PIO2_9 register (IOCON_PIO2_9,
address 0x4004 4054) bit description . . . . . .101
Table 117. IOCON_PIO2_10 register (IOCON_PIO2_10,
address 0x4004 4058) bit description . . . . . .101
Table 118. IOCON_PIO2_2 register (IOCON_PIO2_2,
address 0x4004 405C) bit description . . . . . .102
Table 119. IOCON_PIO0_8 register (IOCON_PIO0_8,
address 0x4004 4060) bit description . . . . . .102
Table 120. IOCON_PIO0_9 register (IOCON_PIO0_9,
address 0x4004 4064) bit description . . . . . .103
Table 121. IOCON_SWCLK_PIO0_10 register
(IOCON_SWCLK_PIO0_10, address 0x4004
4068) bit description . . . . . . . . . . . . . . . . . . .104
Table 122. IOCON_PIO1_10 register (IOCON_PIO1_10,
address 0x4004 406C) bit description . . . . . .104
Table 123. IOCON_PIO2_11 register (IOCON_PIO2_11,
address 0x4004 4070) bit description . . . . . .105
Table 124. IOCON_R_PIO0_11 register
(IOCON_R_PIO0_11, address 0x4004 4074) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Table 125. IOCON_R_PIO1_0 register (IOCON_R_PIO1_0,
address 0x4004 4078) bit description . . . . . .106
Table 126. IOCON_R_PIO1_1 register (IOCON_R_PIO1_1,
address 0x4004 407C) bit description . . . . . .107
Table 127. IOCON_R_PIO1_2 register (IOCON_R_PIO1_2,
address 0x4004 4080) bit description . . . . . .108
Table 128. IOCON_PIO3_0 register (IOCON_PIO3_0,
address 0x4004 4084) bit description . . . . . .109
Table 129. IOCON_PIO3_1 register (IOCON_PIO3_1,
address 0x4004 4088) bit description . . . . . .109
Table 130. IOCON_PIO2_3 register (IOCON_PIO2_3,
address 0x4004 408C) bit description . . . . . .110
Table 131. IOCON_SWDIO_PIO1_3 register
(IOCON_SWDIO_PIO1_3, address 0x4004 4090)
bit description . . . . . . . . . . . . . . . . . . . . . . . .110
Table 132. IOCON_PIO1_4 register (IOCON_PIO1_4,
address 0x4004 4094) bit description . . . . . . 111
Table 133. IOCON_PIO1_11 register (IOCON_PIO1_11,
address 0x4004 4098) bit description . . . . . .112
Table 134. IOCON_PIO3_2 register (IOCON_PIO3_2,
address 0x4004 409C) bit description . . . . .113
Table 135. IOCON_PIO1_5 register (IOCON_PIO1_5,
address 0x4004 40A0) bit description . . . . . .113
Table 136. IOCON_PIO1_6 register (IOCON_PIO1_6,
address 0x4004 40A4) bit description . . . . . .114
Table 137. IOCON_PIO1_7 register (IOCON_PIO1_7,
address 0x4004 40A8) bit description . . . . . . 114
Table 138. IOCON_PIO3_3 register (IOCON_PIO3_3,
address 0x4004 40AC) bit description . . . . . 115
Table 139. IOCON SCK0 location register
(IOCON_SCK0_LOC, address 0x4004 40B0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 140. IOCON DSR location register
(IOCON_DSR_LOC, address 0x4004 40B4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 141. IOCON DCD location register
(IOCON_DCD_LOC, address 0x4004 40B8) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 142. IOCON RI location register (IOCON_RI_LOC,
address 0x4004 40BC) bit description . . . . . 117
Table 143. LPC13xx pin configuration overview. . . . . . . 118
Table 144. LPC1313/42/43 LQFP48 pin description table .
123
Table 145. LPC1311/13/42/43 HVQFN33 pin description
table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 146. GPIO configuration . . . . . . . . . . . . . . . . . . . . 130
Table 147. GPIO pin description
[1]
. . . . . . . . . . . . . . . . . 130
Table 148. Register overview: GPIO (base address port 0:
0x5000 0000; port 1: 0x5001 0000, port 2: 0x5002
0000; port 3: 0x5003 0000) . . . . . . . . . . . . . . 131
Table 149. GPIO data register (GPIO0DATA, address
0x5000 3FFC; GPIO1DATA, address 0x5001
3FFC; GPIO2DATA, address 0x5002 3FFC;
GPIO3DATA, address 0x5003 3FFC) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 150. GPIO data direction register (GPIO0DIR, address
0x5000 8000 to GPIO3DIR, address 0x5003
8000) bit description . . . . . . . . . . . . . . . . . . . 132
Table 151. GPIO interrupt sense register (GPIO0IS, address
0x5000 8004 to GPIO3IS, address 0x5003 8004)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 152. GPIO interrupt both edges sense register
(GPIO0IBE, address 0x5000 8008 to GPIO3IBE,
address 0x5003 8008) bit description . . . . . . 133
Table 153. GPIO interrupt event register (GPIO0IEV,
address 0x5000 800C to GPIO3IEV, address
0x5003 800C) bit description . . . . . . . . . . . . 133
Table 154. GPIO interrupt mask register (GPIO0IE, address
0x5000 8010 to GPIO3IE, address 0x5003 8010)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 155. GPIO raw interrupt status register (GPIO0RIS,
address 0x5000 8014 to GPIO3RIS, address
0x5003 8014) bit description . . . . . . . . . . . . . 134
Table 156. GPIO masked interrupt status register
(GPIO0MIS, address 0x5000 8018 to GPIO3MIS,
address 0x5003 8018) bit description . . . . . . 134
Table 157. GPIO interrupt clear register (GPIO0IC, address
0x5000 801C to GPIO3IC, address 0x5003 801C)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 158. USB related acronyms, abbreviations, and
definitions used in this chapter. . . . . . . . . . . . 136
Table 159. Fixed endpoint configuration . . . . . . . . . . . . . 137
Table 160. USB device pin description . . . . . . . . . . . . . . 140

NXP Semiconductors LPC1311 Specifications

General

Brand	NXP Semiconductors
Model	LPC1311
Category	Controller
Language	English