NXP Semiconductors LPC1311 - USB Device Interrupt Enable Register (Usbdevinten - 0 X4002 0004); Reserved

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User manual Rev. 3 — 14 June 2011 144 of 368
NXP Semiconductors
UM10375
Chapter 10: LPC13xx USB device controller
10.10.1.2 USB Device Interrupt Enable register (USBDevIntEn - 0x4002 0004)
Writing a one to a bit in this register enables the corresponding bit in USBDevIntSt to
generate an external interrupt when set. If it’s not set, no external interrupt is generated,
but the interrupt will still be held in the Device Interrupt Status register.
4 EP3 USB core interrupt for physical endpoint 3.
0 = no interrupt.
1 = interrupt pending.
-
5 EP4 USB core interrupt for physical endpoint 4.
0 = no interrupt.
1 = interrupt pending.
-
6 EP5 USB core interrupt for physical endpoint 5.
0 = no interrupt.
1 = interrupt pending.
-
7 EP6 USB core interrupt for physical endpoint 6.
0 = no interrupt.
1 = interrupt pending.
-
8 EP7 USB core interrupt for physical endpoint 7.
0 = no interrupt.
1 = interrupt pending.
-
9 DEV_STAT Set when USB Bus reset, USB suspend change, or Connect
change event occurs. Refer to Section 10.11.7
.
0 = no interrupt.
1 = interrupt pending.
0
10 CC_EMPTY The command code register (USBCmdCode) is empty (New
command can be written).
0 = no interrupt.
1 = interrupt pending.
1
11 CD_FULL Command data register (USBCmdData) is full (Data can be read
now).
0 = no interrupt.
1 = interrupt pending.
0
12 RxENDPKT The current packet in the endpoint buffer is transferred to the
CPU.
0 = no interrupt.
1 = interrupt pending.
0
13 TxENDPKT The number of data bytes transferred to the endpoint buffer
equals the number of bytes programmed in the TxPacket length
register (USBTxPLen).
0 = no interrupt.
1 = interrupt pending.
0
31:14 - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
-
Table 163. USB Device Interrupt Status register (USBDevIntSt - address 0x4002 0000) bit
description
…continued
Bit Symbol Description Reset
value