UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 146 of 368
NXP Semiconductors
UM10375
Chapter 10: LPC13xx USB device controller
10.10.1.3 USB Device Interrupt Clear register (USBDevIntClr - 0x4002 0008)
Writing one to a bit in this register clears the corresponding bit in USBDevIntSt. Writing a
zero has no effect.
USBDevIntClr is a write only register.
11 CD_FULL_EN Command data register (USBCmdData) is full (Data can be
read now).
0 = no interrupt generated.
1 = interrupt generated when the corresponding bit in
USBDevIntSt is set.
0
12 RXENDPKT_EN The current packet in the endpoint buffer is transferred to
the CPU.
0 = no interrupt generated.
1 = interrupt generated when the corresponding bit in
USBDevIntSt is set.
0
13 TXENDPKT_EN The number of data bytes transferred to the endpoint buffer
equals the number of bytes programmed in the TxPacket
length register (USBTxPLen).
0 = no interrupt generated.
1 = interrupt generated when the corresponding bit in
USBDevIntSt is set.
0
31:14 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
-
Table 164. USB Device Interrupt Enable register (USBDevIntEn - address 0x4002 0004) bit
description
Bit Symbol Description Reset
value
Table 165. USB Device Interrupt Clear register (USBDevIntClr - address 0x4002 0008) bit
description
Bit Symbol Description Reset
value
0 FRAME_CLR Frame interrupt. For isochronous packet transfers.
0 = no effect.
1 = the corresponding bit in USBDevIntSt is cleared.
0
1 EP0_CLR USB core interrupt for physical endpoint 0.
0 = no effect.
1 = the corresponding bit in USBDevIntSt is cleared.
0
2 EP1_CLR USB core interrupt for physical endpoint 1.
0 = no effect.
1 = the corresponding bit in USBDevIntSt is cleared.
0
3 EP2_CLR USB core interrupt for physical endpoint 2.
0 = no effect.
1 = the corresponding bit in USBDevIntSt is cleared.
0
4 EP3_CLR USB core interrupt for physical endpoint 3.
0 = no effect.
1 = the corresponding bit in USBDevIntSt is cleared.
0
5 EP4_CLR USB core interrupt for physical endpoint 4.
0 = no effect.
1 = the corresponding bit in USBDevIntSt is cleared.
0
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