UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 189 of 368
NXP Semiconductors
UM10375
Chapter 12: LPC13xx UART
12.6.8 UART Modem Control Register
The U0MCR enables the modem loopback mode and controls the modem output signals.
3 PE Parity Enable 0
0 Disable parity generation and checking.
1 Enable parity generation and checking.
5:4 PS Parity Select 0
0x0 Odd parity. Number of 1s in the transmitted character and the
attached parity bit will be odd.
0x1 Even Parity. Number of 1s in the transmitted character and the
attached parity bit will be even.
0x2 Forced 1 stick parity.
0x3 Forced 0 stick parity.
6BC Break Control 0
0 Disable break transmission.
1 Enable break transmission. Output pin UART TXD is forced to logic
0 when U0LCR[6] is active high.
7 DLAB Divisor Latch Access Bit (DLAB) 0
0 Disable access to Divisor Latches.
1 Enable access to Divisor Latches.
31:
8
- - Reserved -
Table 202. UART Line Control Register (U0LCR - address 0x4000 800C) bit description
Bit Symbol Value Description Reset
Value
Table 203. UART0 Modem Control Register (U0MCR - address 0x4000 8010) bit description
Bit Symbol Value Description Reset
value
0 DTRCTRL Source for modem output pin, DTR. This bit reads as 0 when
modem loopback mode is active.
0
1 RTSCTRL Source for modem output pin RTS
. This bit reads as 0 when
modem loopback mode is active.
0
3:2 - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
0
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