UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 315 of 368
NXP Semiconductors
UM10375
Chapter 20: LPC13xx Analog-to-Digital Converter (ADC)
20.6.2 A/D Global Data Register (AD0GDR - 0x4001 C004)
The A/D Global Data Register contains the result of the most recent A/D conversion. This
includes the data, DONE, and Overrun flags, and the number of the A/D channel to which
the data relates.
0x4 Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0. Timer
match function does not need to be selected on the device pin.
0x5 Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1. Timer
match function does not need to be selected on the device pin.
0x6 Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0. Timer
match function does not need to be selected on the device pin.
0x7 Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1. Timer
match function does not need to be selected on the device pin.
27 EDGE This bit is significant only when the START field contains 010-111. In these cases: 0
0 Start conversion on a rising edge on the selected CAP/MAT signal.
1 Start conversion on a falling edge on the selected CAP/MAT signal.
31:28 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 305: A/D Control Register (AD0CR - address 0x4001 C000) bit description
Bit Symbol Value Description Reset
Value
Table 306: A/D Global Data Register (AD0GDR - address 0x4001 C004) bit description
Bit Symbol Description Reset
Value
5:0 - Reserved. 0
15:6 V_VREF When DONE is 1, this field contains a binary fraction representing the
voltage on the ADn pin selected by the SEL field, divided by the voltage
on the V
DD
pin. Zero in the field indicates that the voltage on the ADn
pin was less than, equal to, or close to that on V
SS
, while 0x3FF
indicates that the voltage on ADn was close to, equal to, or greater than
that on V
REF
.
X
23:16 - Reserved. 0
26:24 CHN These bits contain the channel from which the V_VREF bits were
converted.
X
29:27 - Reserved. 0
30 OVERR
UN
This bit is 1 in burst mode if the results of one or more conversions was
(were) lost and overwritten before the conversion that produced the
result in the V_VREF bits.
0
31 DONE This bit is set to 1 when an A/D conversion completes. It is cleared
when this register is read and when the ADCR is written. If the ADCR is
written while a conversion is still in progress, this bit is set and a new
conversion is started.
0
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