NXP Semiconductors LPC1311 User Manual

UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 253 of 368
NXP Semiconductors
UM10375
Chapter 14: LPC13xx SSP0/1
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
SSP1CPSR R/W 0x010 Clock Prescale Register. 0
SSP1IMSC R/W 0x014 Interrupt Mask Set and Clear Register. 0
SSP1RIS RO 0x018 Raw Interrupt Status Register. 0x0000
0008
SSP1MIS RO 0x01C Masked Interrupt Status Register. 0
SSP1ICR WO 0x020 SSPICR Interrupt Clear Register. NA
Table 242. Register overview: SSP1 (base address 0x4005 8000)
Name Access Address
offset
Description Reset
value
[1]

NXP Semiconductors LPC1311 Specifications

General

Brand	NXP Semiconductors
Model	LPC1311
Category	Controller
Language	English