NXP Semiconductors LPC1311 User Manual

UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 20 of 368
NXP Semiconductors
UM10375
Chapter 3: LPC13xx System configuration
3.5.7 System oscillator control register
This register configures the frequency range for the system oscillator.
3.5.8 Watchdog oscillator control register
This register configures the watchdog oscillator. The oscillator consists of an analog and a
digital part. The analog part contains the oscillator function and generates an analog clock
(Fclkana). With the digital part, the analog output clock (Fclkana) can be divided to the
required output clock frequency wdt_osc_clk. The analog output frequency (Fclkana) can
be adjusted with the FREQSEL bits between 500 kHz and 3.4 MHz. With the digital part
Fclkana will be divided (divider ratios = 2, 4,...,64) to wdt_osc_clk using the DIVSEL bits.
The output clock frequency of the watchdog oscillator can be calculated as
wdt_osc_clk = Fclkana/(2  (1 + DIVSEL)) = 7.8 kHz to 1.7 MHz (nominal values).
Remark: Any setting of the FREQSEL bits will yield a Fclkana value within  40% of the
listed frequency value. The watchdog oscillator is the clock source with the lowest power
consumption. If accurate timing is required, use the IRC or system clock.
Remark: The frequency of the watchdog oscillator is undefined after reset. The watchdog
oscillator frequency must be programmed by writing to the WDTOSCCTRL register before
using the watchdog oscillator.
Table 14. System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit
description
Bit Symbol Value Description Reset
value
0 BYPASS Bypass system oscillator 0x0
0 Oscillator is not bypassed.
1 Bypass enabled. PLL input (sys_osc_clk) is fed
directly from the XTALIN and XTALOUT pins.
1 FREQRANGE Determines frequency range for Low-power
oscillator.
0x0
0 1 - 20 MHz frequency range.
1 15 - 25 MHz frequency range
31:2 - - Reserved 0x00
Table 15. Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit
description
Bit Symbol Value Description Reset
value
4:0 DIVSEL Select divider for Fclkana.
wdt_osc_clk = Fclkana/(2  (1 + DIVSEL)).
00000: 2  (1 + DIVSEL) = 2
00001: 2  (1 + DIVSEL) = 4
to
11111: 2  (1 + DIVSEL) = 64
0x0

NXP Semiconductors LPC1311 Specifications

General

Brand	NXP Semiconductors
Model	LPC1311
Category	Controller
Language	English