NXP Semiconductors LPC1311 User Manual

UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 30 of 368
NXP Semiconductors
UM10375
Chapter 3: LPC13xx System configuration
3.5.27 WDT clock source select register
This register selects the clock source for the watchdog timer. The WDTCLKUEN register
(see Section 3.5.28
) must be toggled from LOW to HIGH for the update to take effect.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated. Once the WWDT (LPC1311/01 and LPC1313/01 only) is enabled, the
watchdog clock source cannot be changed. If the watchdog timer is running in Deep-sleep
mode, always select the watchdog oscillator as clock source (see Section 3.9.3.2
).
3.5.28 WDT clock source update enable register
This register updates the clock source of the watchdog timer with the new input clock after
the WDTCLKSEL register has been written to. In order for the update to take effect at the
input of the watchdog timer, first write a zero to the WDTCLKUEN register and then write
a one to WDTCLKUEN.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
3.5.29 WDT clock divider register
This register determines the divider values for the watchdog clock wdt_clk.
Table 34. WDT clock source select register (WDTCLKSEL, address 0x4004 80D0) bit
description
Bit Symbol Value Description Reset
value
1:0 SEL WDT clock source 0x00
0x0 IRC oscillator
0x1 Main clock
0x2 Watchdog oscillator
0x3 Reserved
31:2 - - Reserved 0x00
Table 35. WDT clock source update enable register (WDTCLKUEN, address 0x4004 80D4)
bit description
Bit Symbol Value Description Reset value
0 ENA Enable WDT clock source update 0x0
0 No change
1 Update clock source
31:1 - - Reserved 0x00
Table 36. WDT clock divider register (WDTCLKDIV, address 0x4004 80D8) bit description
Bit Symbol Description Reset value
7:0 DIV WDT clock divider values.
0: Disable WDCLK.
1: Divide by 1.
to
255: Divide by 255.
0x00
31:8 - Reserved 0x00

NXP Semiconductors LPC1311 Specifications

General

Brand	NXP Semiconductors
Model	LPC1311
Category	Controller
Language	English