UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 23 of 368
NXP Semiconductors
UM10375
Chapter 3: LPC13xx System configuration
3.5.12 System PLL clock source update enable register
This register updates the clock source of the system PLL with the new input clock after the
SYSPLLCLKSEL register has been written to. In order for the update to take effect, first
write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
3.5.13 USB PLL clock source select register
This register selects the clock source for the dedicated USB PLL. The USBPLLCLKUEN
register (see Section 3.5.14
) must be toggled from LOW to HIGH for the update to take
effect.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated in the USBPLLCLKUEN register. For USB operation, the clock source
must be switched from IRC to system oscillator with both the IRC and the system
oscillator running. After the switch, the IRC can be turned off.
Table 18. System PLL clock source select register (SYSPLLCLKSEL, address 0x4004 8040)
bit description
Bit Symbol Value Description Reset
value
1:0 SEL System PLL clock source 0x00
0x0 IRC oscillator
0x1 System oscillator
0x2 Reserved
0x3 Reserved
31:2 - - Reserved 0x00
Table 19. System PLL clock source update enable register (SYSPLLCLKUEN, address
0x4004 8044) bit description
Bit Symbol Value Description Reset value
0 ENA Enable system PLL clock source update 0x0
0 No change
1 Update clock source
31:1 - - Reserved 0x00
Table 20. USB PLL clock source select register (USBPLLCLKSEL, address 0x4004 8048) bit
description
Bit Symbol Value Description Reset
value
1:0 SEL USB PLL clock source 0x00
0x0 IRC. The USB PLL clock source must be switched to system
oscillator for correct USB operation.
0x1 System oscillator
0x2 Reserved
0x3 Reserved
31:2 - - Reserved 0x00