UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 52 of 368
4.1 Introduction
The PMU controls the Deep power-down mode. Four general purpose register in the PMU
can be used to retain data during Deep power-down mode.
4.2 Register description
4.2.1 Power control register
The power control register selects whether one of the ARM Cortex-M3 controlled
power-down modes (Sleep mode or Deep-sleep mode) or the Deep power-down mode is
entered and provides the flags for Sleep or Deep-sleep modes and Deep power-down
modes respectively. See Section 3.9
for details on how to enter the power-down modes.
UM10375
Chapter 4: LPC13xx Power Management Unit (PMU)
Rev. 3 — 14 June 2011 User manual
Table 60. Register overview: PMU (base address 0x4003 8000)
Name Access Address
offset
Description Reset
value
PCON R/W 0x000 Power control register 0x0
GPREG0 R/W 0x004 General purpose register 0 0x0
GPREG1 R/W 0x008 General purpose register 1 0x0
GPREG2 R/W 0x00C General purpose register 2 0x0
GPREG3 R/W 0x010 General purpose register 3 0x0
GPREG4 R/W 0x014 General purpose register 4 0x0
Table 61. Power control register (PCON, address 0x4003 8000) bit description
Bit Symbol Value Description Reset
value
0 - - Reserved. Do not write 1 to this bit. 0x0
1 DPDEN Deep power-down mode enable 0
0 ARM WFI will enter Sleep or Deep-sleep mode (clock to
ARM Cortex-M3 core turned off).
1 ARM WFI will enter Deep-power down mode (ARM
Cortex-M3 core powered-down).
7:2 - - Reserved. Do not write ones to this bit. 0x0
8 SLEEPFLAG Sleep mode flag 0
0 Read: No power-down mode entered. LPC13xx is in Run
mode.
Write: No effect.
1 Read: Sleep/Deep-sleep or Deep power-down mode
entered.
Write: Writing a 1 clears the SLEEPFLAG bit to 0.
10:9 - - Reserved. Do not write ones to this bit. 0x0
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