NXP Semiconductors LPC1311 User Manual

UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 360 of 368
NXP Semiconductors
UM10375
Chapter 23: LPC13xx Supplementary information
23.5 Contents
Chapter 1: LPC13xx Introductory information
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 How to read this manual . . . . . . . . . . . . . . . . . . 3
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 5
1.5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 2: LPC13xx Memory mapping
2.1 How to read this chapter. . . . . . . . . . . . . . . . . . 8
2.2 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Memory remapping. . . . . . . . . . . . . . . . . . . . . . 9
Chapter 3: LPC13xx System configuration
3.1 How to read this chapter. . . . . . . . . . . . . . . . . 10
USB clocking and power control. . . . . . . . . . . .10
SSP1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
BOD control . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Input pins to the start logic . . . . . . . . . . . . . . . .11
PIO reset status registers. . . . . . . . . . . . . . . . .11
Entering Deep power-down mode . . . . . . . . . .11
Enabling sequence for UART clock . . . . . . . . .11
3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Pin description. . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Clocking and power control . . . . . . . . . . . . . . 13
3.5 Register description . . . . . . . . . . . . . . . . . . . . 14
3.5.1 System memory remap register . . . . . . . . . . . 16
3.5.2 Peripheral reset control register . . . . . . . . . . . 17
3.5.3 System PLL control register . . . . . . . . . . . . . . 17
3.5.4 System PLL status register. . . . . . . . . . . . . . . 18
3.5.5 USB PLL control register . . . . . . . . . . . . . . . . 18
3.5.6 USB PLL status register . . . . . . . . . . . . . . . . . 19
3.5.7 System oscillator control register . . . . . . . . . . 20
3.5.8 Watchdog oscillator control register . . . . . . . . 20
3.5.9 Internal resonant crystal control register. . . . . 21
3.5.10 System reset status register. . . . . . . . . . . . . . 22
3.5.11 System PLL clock source select register . . . . 22
3.5.12 System PLL clock source update enable
register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5.13 USB PLL clock source select register. . . . . . . 23
3.5.14 USB PLL clock source update enable register 24
3.5.15 Main clock source select register . . . . . . . . . . 24
3.5.16 Main clock source update enable register . . . 24
3.5.17 System AHB clock divider register . . . . . . . . . 25
3.5.18 System AHB clock control register . . . . . . . . . 25
3.5.19 SSP0 clock divider register. . . . . . . . . . . . . . . 27
3.5.20 UART clock divider register . . . . . . . . . . . . . . 27
3.5.21 SSP1 clock divider register. . . . . . . . . . . . . . . 28
3.5.22 Trace clock divider register. . . . . . . . . . . . . . . 28
3.5.23 SYSTICK clock divider register. . . . . . . . . . . . 28
3.5.24 USB clock source select register . . . . . . . . . . 28
3.5.25 USB clock source update enable register. . . . 29
3.5.26 USB clock divider register. . . . . . . . . . . . . . . . 29
3.5.27 WDT clock source select register . . . . . . . . . . 30
3.5.28 WDT clock source update enable register . . . 30
3.5.29 WDT clock divider register . . . . . . . . . . . . . . . 30
3.5.30 CLKOUT clock source select register . . . . . . 31
3.5.31 CLKOUT clock source update enable register 31
3.5.32 CLKOUT clock divider register. . . . . . . . . . . . 31
3.5.33 POR captured PIO status register 0 . . . . . . . 32
3.5.34 POR captured PIO status register 1 . . . . . . . 32
3.5.35 BOD control register . . . . . . . . . . . . . . . . . . . 33
3.5.36 System tick counter calibration register . . . . . 33
3.5.37 Start logic edge control register 0 . . . . . . . . . 34
3.5.38 Start logic signal enable register 0. . . . . . . . . 34
3.5.39 Start logic reset register 0 . . . . . . . . . . . . . . . 35
3.5.40 Start logic status register 0 . . . . . . . . . . . . . . 35
3.5.41 Start logic edge control register 1 . . . . . . . . . 35
3.5.42 Start logic signal enable register 1. . . . . . . . . 36
3.5.43 Start logic reset register 1 . . . . . . . . . . . . . . . 36
3.5.44 Start logic status register 1 . . . . . . . . . . . . . . 37
3.5.45 Deep-sleep mode configuration register . . . . 37
3.5.46 Wake-up configuration register . . . . . . . . . . . 38
3.5.47 Power-down configuration register . . . . . . . . 39
3.5.48 Device ID register . . . . . . . . . . . . . . . . . . . . . 41
3.6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.7 Start-up behavior. . . . . . . . . . . . . . . . . . . . . . . 41
3.8 Brown-out detection . . . . . . . . . . . . . . . . . . . . 42
3.9 Power management . . . . . . . . . . . . . . . . . . . . 42
3.9.1 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.9.1.1 Power configuration in Active mode. . . . . . . . 43
3.9.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.9.2.1 Power configuration in Sleep mode . . . . . . . . 43
3.9.2.2 Programming Sleep mode . . . . . . . . . . . . . . . 43
3.9.2.3 Wake-up from Sleep mode . . . . . . . . . . . . . . 44
3.9.3 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 44
3.9.3.1 Power configuration in Deep-sleep mode . . . 44
3.9.3.2 Programming Deep-sleep mode . . . . . . . . . . 44
3.9.3.3 Wake-up from Deep-sleep mode . . . . . . . . . . 45
3.9.4 Deep power-down mode . . . . . . . . . . . . . . . . 45
3.9.4.1 Power configuration in Deep power-down
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.9.4.2 Programming Deep power-down mode . . . . . 46
3.9.4.3 Wake-up from Deep power-down mode . . . . 46
3.10 Deep-sleep mode details . . . . . . . . . . . . . . . . 46
3.10.1 IRC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.10.2 Start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

NXP Semiconductors LPC1311 Specifications

General

Brand	NXP Semiconductors
Model	LPC1311
Category	Controller
Language	English