UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 355 of 368
NXP Semiconductors
UM10375
Chapter 23: LPC13xx Supplementary information
Table 161. USB device controller clock sources . . . . . . .141
Table 162. Register overview: USB device (base address
0x4002 0000) . . . . . . . . . . . . . . . . . . . . . . . . .143
Table 163. USB Device Interrupt Status register
(USBDevIntSt - address 0x4002 0000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . .143
Table 164. USB Device Interrupt Enable register
(USBDevIntEn - address 0x4002 0004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .145
Table 165. USB Device Interrupt Clear register
(USBDevIntClr - address 0x4002 0008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .146
Table 166. USB Device Interrupt Set register (USBDevIntSet
- address 0x4002 000C) bit description . . . . .148
Table 167. USB Command Code register (USBCmdCode -
address 0x4002 0010) bit description. . . . . . .149
Table 168. USB Command Data register (USBCmdData -
address 0x4002 0014) bit description. . . . . . .150
Table 169. USB Receive Data register (USBRxData -
address 0x4002 0018) bit description. . . . . . .150
Table 170. USB Transmit Data register (USBTxData -
address 0x4002 001C) bit description . . . . . .150
Table 171. USB Receive Packet Length register
(USBRxPLen - address 0x4002 0020) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Table 172. USB Transmit Packet Length register
(USBTxPLen - address 0x4002 0024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Table 173. USB Control register (USBCtrl - address 0x4002
0028) bit description . . . . . . . . . . . . . . . . . . . .152
Table 174. USB Device FIQ Select register (USBDevFIQSel
- address 0x4002 002C) bit description . . . . .153
Table 175. SIE command code table. . . . . . . . . . . . . . . .154
Table 176. Device Set Address command description . .155
Table 177. Configure Device command description . . . .156
Table 178. Set Mode command description . . . . . . . . . .156
Table 179. Read interrupt Status byte 1 command
description . . . . . . . . . . . . . . . . . . . . . . . . . . .156
Table 180. Read interrupt Status byte 2 command
description . . . . . . . . . . . . . . . . . . . . . . . . . . .157
Table 181. Set Device Status command description . . . .157
Table 182. Get Error Code command description . . . . . .159
Table 183. Select Endpoint command description. . . . . .159
Table 184. Set Endpoint Status command description . .161
Table 185. Clear Buffer command description. . . . . . . . .162
Table 186. USB device information class structure . . . . .173
Table 187. Mass storage device information class
structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
Table 188. Human interface device information class
structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
Table 189. Standard descriptor . . . . . . . . . . . . . . . . . . . .175
Table 190. Mass storage descriptors. . . . . . . . . . . . . . . .176
Table 191. HID descriptors . . . . . . . . . . . . . . . . . . . . . . .177
Table 192. UART pin description. . . . . . . . . . . . . . . . . . .180
Table 193. Register overview: UART (base address: 0x4000
8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
Table 194. UART Receiver Buffer Register (U0RBR -
address 0x4000 8000 when DLAB = 0, Read
Only) bit description . . . . . . . . . . . . . . . . . . . 183
Table 195. UART Transmitter Holding Register (U0THR -
address 0x4000 8000 when DLAB = 0, Write
Only) bit description . . . . . . . . . . . . . . . . . . . . 183
Table 196. UART Divisor Latch LSB Register (U0DLL -
address 0x4000 8000 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 197. UART Divisor Latch MSB Register (U0DLM -
address 0x4000 8004 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 198. UART Interrupt Enable Register (U0IER -
address 0x4000 8004 when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 199. UART Interrupt Identification Register (U0IIR -
address 0x4004 8008, Read Only) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 200. UART Interrupt Handling. . . . . . . . . . . . . . . . 186
Table 201. UART FIFO Control Register (U0FCR - address
0x4000 8008, Write Only) bit description. . . . 188
Table 202. UART Line Control Register (U0LCR - address
0x4000 800C) bit description . . . . . . . . . . . . 188
Table 203. UART0 Modem Control Register (U0MCR -
address 0x4000 8010) bit description . . . . . . 189
Table 204. Modem status interrupt generation . . . . . . . . 191
Table 205. UART Line Status Register (U0LSR - address
0x4000 8014, Read Only) bit description . . . 192
Table 206. UART Modem Status Register (U0MSR - address
0x4000 8018) bit description . . . . . . . . . . . . . 194
Table 207. UART Scratch Pad Register (U0SCR - address
0x4000 801C) bit description . . . . . . . . . . . . . 194
Table 208. Auto-baud Control Register (U0ACR - address
0x4000 8020) bit description . . . . . . . . . . . . . 195
Table 209. UART Fractional Divider Register (U0FDR -
address 0x4000 8028) bit description . . . . . . 198
Table 210. Fractional Divider setting look-up table. . . . . 201
Table 211. UART Transmit Enable Register (U0TER -
address 0x4000 8030) bit description . . . . . . 202
Table 212. UART RS485 Control register (U0RS485CTRL -
address 0x4000 804C) bit description . . . . . 202
Table 213. UART RS-485 Address Match register
(U0RS485ADRMATCH - address 0x4000 8050)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 214. UART RS-485 Delay value register
(U0RS485DLY - address 0x4000 8054) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 215. I
2
C-bus pin description . . . . . . . . . . . . . . . . . 209
Table 216. Register overview: I
2
C (base address 0x4000
0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 217. I
2
C Control Set register (I2C0CONSET - address
0x4000 0000) bit description . . . . . . . . . . . . . 210
Table 218. I
2
C Status register (I2C0STAT - 0x4000 0004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 219. I
2
C Data register (I2C0DAT - 0x4000 0008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 220. I
2
C Slave Address register 0 (I2C0ADR0-
0x4000 000C) bit description . . . . . . . . . . . . . 213
Table 221. I
2
C SCL HIGH Duty Cycle register (I2C0SCLH -
address 0x4000 0010) bit description . . . . . . 213
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