UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 39 of 368
NXP Semiconductors
UM10375
Chapter 3: LPC13xx System configuration
3.5.47 Power-down configuration register
The bits in the PDRUNCFG register control the power to the various analog blocks. This
register can be written to at any time while the chip is running, and a write will take effect
immediately with the exception of the power-down signal to the IRC.
To avoid glitches when powering down the IRC, the IRC clock is automatically switched off
at a clean point. Therefore, for the IRC a delay is possible before the power-down state
takes effect.
1 IRC_PD IRC oscillator power-down wake-up configuration 0
0 Powered
1 Powered down
2 FLASH_PD Flash wake-up configuration 0
0 Powered
1 Powered down
3 BOD_PD BOD wake-up configuration 0
0 Powered
1 Powered down
4 ADC_PD ADC wake-up configuration 1
0 Powered
1 Powered down
5 SYSOSC_PD System oscillator wake-up configuration 1
0 Powered
1 Powered down
6 WDTOSC_PD Watchdog oscillator wake-up configuration 1
0 Powered
1 Powered down
7 SYSPLL_PD System PLL wake-up configuration 1
0 Powered
1 Powered down
8 USBPLL_PD USB PLL wake-up configuration 1
0 Powered
1 Powered down
9 FIXEDVAL - Reserved. Always write this bit as 0. 0
10 USBPAD_PD USB pad wake-up configuration 1
0 USB PHY powered
1 USB PHY powered down
11 FIXEDVAL - Reserved. Always write this bit as 1. 1
31:12 - - Reserved 0
Table 54. Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit
description
…continued
Bit Symbol Value Description Reset
value
To Next Page
Loading...
Need help?
General
