UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 267 of 368
NXP Semiconductors
UM10375
Chapter 15: LPC13xx 16-bit timer/counters (CT16B0/1)
15.5 Description
Each Counter/timer is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and can optionally generate interrupts or perform other actions at
specified timer values based on four match registers. Each counter/timer also includes
one capture input to trap the timer value when an input signal transitions, optionally
generating an interrupt.
In PWM mode, three match registers on CT16B0 and two match registers on CT16B1 can
be used to provide a single-edge controlled PWM output on the match output pins. It is
recommended to use the match registers that are not pinned out to control the PWM cycle
length.
Remark: The 16-bit counter/timer0 (CT16B0) and the 16-bit counter/timer1 (CT16B1) are
functionally identical except for the peripheral base address.
15.6 Pin description
Table 252 gives a brief summary of each of the counter/timer related pins.
15.7 Clocking and power control
The peripheral clocks (PCLK) to the 16-bit timers are provided by the system clock (see
Figure 3
). These clocks can be disabled through bit 7 and 8 in the SYSAHBCLKCTRL
register (Table 25
) for power savings.
15.8 Register description
The 16-bit counter/timer0 contains the registers shown in Table 253 and the 16-bit
counter/timer1 contains the registers shown in Table 254
. More detailed descriptions
follow.
Table 252. Counter/timer pin description
Pin Type Description
CT16B0_CAP0
CT16B1_CAP0
Input Capture Signal:
A transition on a capture pin can be configured to load the Capture Register with the
value in the counter/timer and optionally generate an interrupt.
Counter/Timer block can select a capture signal as a clock source instead of the PCLK
derived clock. For more details see Section 15.8.11
.
CT16B0_MAT[2:0]
CT16B1_MAT[1:0]
Output External Match Outputs of CT16B0/1:
When a match register of CT16B0/1 (MR3:0) equals the timer counter (TC), this output
can either toggle, go LOW, go HIGH, or do nothing. The External Match Register
(EMR) and the PWM Control Register (PWMCON) control the functionality of this
output.
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