UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 327 of 368
NXP Semiconductors
UM10375
Chapter 21: LPC13xx Flash memory programming firmware
In case a CRP mode is enabled and access to the chip is allowed via the ISP, an
unsupported or restricted ISP command will be terminated with return code
CODE_READ_PROTECTION_ENABLED.
21.12.1 ISP entry protection
In addition to the three CRP modes, the user can prevent the sampling of pin PIO0_1 for
entering ISP mode and thereby release pin PIO0_1 for other uses. This is called the
NO_ISP mode. The NO_ISP mode can be entered by programming the pattern
0x4E69 7370 at location 0x0000 02FC.
The NO_ISP mode is identical to the CRP3 mode except for SWD access, which is
allowed in NO_ISP mode but disabled in CRP3 mode. The NO_ISP mode does not offer
any code protection.
CRP2 Yes High No No NA
CRP2 Yes Low No Yes No
CRP3Yesx NoNoNA
CRP1 No x No Yes Yes
CRP2 No x No Yes No
CRP3 No x No Yes No
Table 316. ISP commands allowed for different CRP levels
ISP command CRP1 CRP2 CRP3 (no entry in ISP
mode allowed)
Unlock yes yes n/a
Set Baud Rate yes yes n/a
Echo yes yes n/a
Write to RAM yes; above 0x1000 0300
only
no n/a
Read Memory no no n/a
Prepare sector(s) for
write operation
yes yes n/a
Copy RAM to flash yes; not to sector 0 no n/a
Go no no n/a
Erase sector(s) yes; sector 0 can only be
erased when all sectors are
erased.
yes; all sectors
only
n/a
Blank check sector(s) no no n/a
Read Part ID yes yes n/a
Read Boot code version yes yes n/a
Compare no no n/a
ReadUID yes yes n/a
Table 315. Code Read Protection hardware/software interaction
…continued
CRP option User Code
Valid
PIO0_1 pin at
reset
SWD enabled LPC13xx
enters ISP
mode
partial flash
Update in ISP
mode
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