UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 229 of 368
NXP Semiconductors
UM10375
Chapter 13: LPC13xx I2C-bus controller
13.11.2 Master Receiver mode
In the master receiver mode, a number of data bytes are received from a slave transmitter
(see Figure 35
). The transfer is initialized as in the master transmitter mode. When the
START condition has been transmitted, the interrupt service routine must load I2DAT with
the 7-bit slave address and the data direction bit (SLA+R). The SI bit in I2CON must then
be cleared before the serial transfer can continue.
When the slave address and the data direction bit have been transmitted and an
acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a
number of status codes in I2STAT are possible. These are 0x40, 0x48, or 0x38 for the
master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = 1). The
appropriate action to be taken for each of these status codes is detailed in Table 236
. After
a Repeated START condition (state 0x10), the I
2
C block may switch to the master
transmitter mode by loading I2DAT with SLA+W.
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