UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 37 of 368
NXP Semiconductors
UM10375
Chapter 3: LPC13xx System configuration
3.5.44 Start logic status register 1
This register reflects the status of the enabled start signals. The bit assignment is identical
to Table 48
.
3.5.45 Deep-sleep mode configuration register
This register controls the behavior of the WatchDog (WD) oscillator and the BOD circuit
when the device enters Deep-sleep mode.
This register must be initialized at least once before entering Deep-sleep mode with
one of the four values shown in Table 52
:
Remark: Failure to initialize and program this register correctly may result in undefined
behavior of the microcontroller. The values listed in Table 52
are the only values allowed
for PDSLEEPCFG register.
To select the appropriate power configuration for Deep-sleep mode, consider the
following:
Table 50. Start logic reset register 1 (STARTRSRP1CLR, address 0x4004 8218) bit
description
Bit Symbol Description Reset
value
3:0 RSRPIO2_n Start signal reset for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit
3 = PIO2_11).
0 = Do nothing..
1 = Write: reset start signal.
0
7:4 RSRPIO3_n Start signal reset for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit
7 = PIO3_3).
0 = Do nothing.
1 = Write: reset start signal.
0
31:8 - Reserved n/a
Table 51. Start logic signal status register 1 (STARTSRP1, address 0x4004 821C) bit
description
Bit Symbol Description Reset
value
3:0 SRPIO2_n Start signal status for start logic input PIO2_n (bit 0 = PIO2_8, ...,
bit 3 = PIO2_11).
0 = No start signal received.
1 = Start signal pending.
0
7:4 SRPIO3_n Start signal status for start logic input PIO3_n (bit 4 = PIO3_0, ...,
bit 7 = PIO3_3).
0 = No start signal received.
1 = Start signal pending.
0
31:8 - Reserved n/a
Table 52. Allowed values for PDSLEEPCFG register
Configuration WD oscillator on WD oscillator off
BOD on PDSLEEPCFG = 0x0000 0FB7 PDSLEEPCFG = 0x0000 0FF7
BOD off PDSLEEPCFG = 0x0000 0FBF PDSLEEPCFG = 0x0000 0FFF