UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 357 of 368
NXP Semiconductors
UM10375
Chapter 23: LPC13xx Supplementary information
Table 273: Timer counter registers (TMR32B0TC, address
0x4001 4008 and TMR32B1TC 0x4001 8008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .284
Table 274: Prescale registers (TMR32B0PR, address
0x4001 400C and TMR32B1PR 0x4001 800C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .285
Table 275: Prescale counter registers (TMR32B0PC,
address 0x4001 4010 and TMR32B1PC
0x4001 8010) bit description . . . . . . . . . . . . .285
Table 276: Match Control Register (TMR32B0MCR -
address 0x4001 4014 and TMR32B1MCR -
address 0x4001 8014) bit description. . . . . . .285
Table 277: Match registers (TMR32B0MR0 to 3, addresses
0x4001 4018 to 24 and TMR32B1MR0 to 3,
addresses 0x4001 8018 to 24) bit description 286
Table 278: Capture Control Register (TMR32B0CCR -
address 0x4001 4028 and TMR32B1CCR -
address 0x4001 8028) bit description. . . . . . .287
Table 279: Capture registers (TMR32B0CR0, addresses
0x4001 402C and TMR32B1CR0, addresses
0x4001 802C) bit description . . . . . . . . . . . . .287
Table 280: External Match Register (TMR32B0EMR -
address 0x4001 403C and TMR32B1EMR -
address0x4001 803C) bit description. . . . . . .288
Table 281. External match control. . . . . . . . . . . . . . . . . .289
Table 282: Count Control Register (TMR32B0CTCR -
address 0x4001 4070 and TMR32B1TCR -
address 0x4001 8070) bit description . . . . . .290
Table 283: PWM Control Register (TMR32B0PWMC -
0x4001 4074 and TMR32B1PWMC - 0x4001
8074) bit description . . . . . . . . . . . . . . . . . . . .290
Table 284. Register overview: system tick timer (base
address 0xE000 E000). . . . . . . . . . . . . . . . . .295
Table 285. System Timer Control and status register (CTRL
- 0xE000 E010) bit description . . . . . . . . . . . .296
Table 286. System Timer Reload value register (LOAD -
0xE000 E014) bit description . . . . . . . . . . . . .296
Table 287. System Timer Current value register (VAL -
0xE000 E018) bit description . . . . . . . . . . . . .297
Table 288. System Timer Calibration value register (CALIB -
0xE000 E01C) bit description. . . . . . . . . . . . .297
Table 289. Register overview: Watchdog timer (base
address 0x4000 4000) . . . . . . . . . . . . . . . . . .301
Table 290. Watchdog Mode register (WDMOD - address
0x4000 4000) bit description . . . . . . . . . . . . .301
Table 291. Watchdog operating modes selection . . . . . .302
Table 292. Watchdog Constant register (WDTC - address
0x4000 4004) bit description . . . . . . . . . . . . .302
Table 293. Watchdog Feed register (WDFEED - address
0x4000 4008) bit description . . . . . . . . . . . . .302
Table 294. Watchdog Timer Value register (WDTV - address
0x4000 000C) bit description . . . . . . . . . . . . .303
Table 295. Register overview: Watchdog timer (base
address 0x4000 4000) . . . . . . . . . . . . . . . . . .307
Table 296: Watchdog Mode register (WDMOD -
0x4000 4000) bit description . . . . . . . . . . . . .307
Table 297. Watchdog operating modes selection . . . . . .308
Table 298: Watchdog Timer Constant register (WDTC -
0x4000 4004) bit description . . . . . . . . . . . . . 309
Table 299: Watchdog Feed register (WDFEED -
0x4000 4008) bit description . . . . . . . . . . . . . 309
Table 300: Watchdog Timer Value register (WDTV -
0x4000 400C) bit description . . . . . . . . . . . . . 309
Table 301: Watchdog Timer Warning Interrupt register
(WDWARNINT - 0x4000 4014) bit description310
Table 302: Watchdog Timer Window register (WDWINDOW
- 0x4000 4018) bit description . . . . . . . . . . . . 310
Table 303. ADC pin description . . . . . . . . . . . . . . . . . . . 312
Table 304. Register overview: ADC (base address 0x4001
C000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Table 305: A/D Control Register (AD0CR - address
0x4001 C000) bit description . . . . . . . . . . . . . 314
Table 306: A/D Global Data Register (AD0GDR - address
0x4001 C004) bit description . . . . . . . . . . . . . 315
Table 307: A/D Interrupt Enable Register (AD0INTEN -
address 0x4001 C00C) bit description. . . . . . 316
Table 308: A/D Data Registers (AD0DR0 to AD0DR7 -
addresses 0x4001 C010 to 0x4001 C02C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Table 309: A/D Status Register (AD0STAT - address
0x4001 C030) bit description . . . . . . . . . . . . . 317
Table 310. LPC13xx flash configurations . . . . . . . . . . . . 318
Table 311. Bootloader versions. . . . . . . . . . . . . . . . . . . . 318
Table 312. CRP levels for USB boot images . . . . . . . . . 323
Table 313. LPC13xx flash sectors . . . . . . . . . . . . . . . . . 325
Table 314. Code Read Protection (CRP) options . . . . . . 326
Table 315. Code Read Protection hardware/software
interaction . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Table 316. ISP commands allowed for different CRP
levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Table 317. ISP command summary . . . . . . . . . . . . . . . . 328
Table 318. ISP Unlock command . . . . . . . . . . . . . . . . . . 328
Table 319. ISP Set Baud Rate command . . . . . . . . . . . . 329
Table 320. ISP Echo command . . . . . . . . . . . . . . . . . . . 329
Table 321. ISP Write to RAM command . . . . . . . . . . . . . 330
Table 322. ISP Read Memory command . . . . . . . . . . . . 330
Table 323. ISP Prepare sector(s) for write operation
command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Table 324. ISP Copy command . . . . . . . . . . . . . . . . . . . 332
Table 325. ISP Go command . . . . . . . . . . . . . . . . . . . . . 332
Table 326. ISP Erase sector command . . . . . . . . . . . . . 333
Table 327. ISP Blank check sector command . . . . . . . . 333
Table 328. ISP Read Part Identification command . . . . . 333
Table 329. LPC13xx device identification numbers . . . . 334
Table 330. ISP Read Boot Code version number
command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Table 331. ISP Compare command . . . . . . . . . . . . . . . . 334
Table 332. ReadUID command. . . . . . . . . . . . . . . . . . . . 335
Table 333. ISP Return Codes Summary. . . . . . . . . . . . . 335
Table 334. IAP Command Summary . . . . . . . . . . . . . . . 337
Table 335. IAP Prepare sector(s) for write operation
command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Table 336. IAP Copy RAM to flash command. . . . . . . . . 338
Table 337. IAP Erase Sector(s) command . . . . . . . . . . . 339
Table 338. IAP Blank check sector(s) command . . . . . . 339
Table 339. IAP Read Part Identification command . . . . . 339
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