UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 156 of 368
NXP Semiconductors
UM10375
Chapter 10: LPC13xx USB device controller
10.11.3 Set Mode (Command: 0xF3, Data: write 1 byte)
10.11.4 Read Interrupt Status (Command: 0xF4, Data: read 2 bytes)
Table 177. Configure Device command description
Bit Symbol Description Reset
value
0 CONF_DEVICE Device is configured. All enabled non-control endpoints will
respond. This bit is cleared by hardware when a bus reset
occurs. When set, the UP_LED signal is driven LOW if the
device is not in the suspended state (SUS=0).
7:1 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
NA
Table 178. Set Mode command description
Bit Symbol Value Description Reset
value
0 AP_CLK Always PLL Clock. 0
0 USB_NEED_CLK is functional; the 48 MHz clock can be
stopped when the device enters suspend state.
1 USB_NEED_CLK is fixed to 1; the 48 MHz clock cannot be
stopped when the device enters suspend state.
1 INAK_CI Interrupt on NAK for Control IN endpoint. 0
0 Only successful transactions generate an interrupt.
1 Both successful and NAKed IN transactions generate interrupts.
2 INAK_CO Interrupt on NAK for Control OUT endpoint. 0
0 Only successful transactions generate an interrupt.
1 Both successful and NAKed OUT transactions generate
interrupts.
3 INAK_AI Interrupt on NAK for Interrupt or bulk IN endpoint. 0
0 Only successful transactions generate an interrupt.
1 Both successful and NAKed IN transactions generate interrupts.
4 INAK_AO Interrupt on NAK for Interrupt or bulk OUT endpoints. 0
0 Only successful transactions generate an interrupt.
1 Both successful and NAKed OUT transactions generate
interrupts.
7:5 - - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
NA
Table 179. Read interrupt Status byte 1 command description
Bit Symbol Description Reset value
0 EP0 EP0 interrupt 0
1 EP1 EP1 interrupt 0
2 EP2 EP2 interrupt 0
3 EP3 EP3 interrupt 0
4 EP4 EP4 interrupt 0
7:5 - reserved -