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NXP Semiconductors LPC1311 User Manual

NXP Semiconductors LPC1311
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UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 3 of 368
1.1 Introduction
The LPC13xx are ARM Cortex-M3 based microcontrollers for embedded applications
featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a
next generation core that offers system enhancements such as enhanced debug features
and a higher level of support block integration.
The LPC13xx operate at CPU frequencies of up to 72 MHz. The ARM Cortex-M3 CPU
incorporates a 3-stage pipeline and uses a Harvard architecture with separate local
instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3
CPU also includes an internal prefetch unit that supports speculative branching.
The peripheral complement of the LPC13xx series includes up to 32 kB of flash memory,
up to 8 kB of data memory, USB Device, one Fast-mode Plus (FM+) I
2
C interface, one
UART, four general purpose timers, and up to 42 general purpose I/O pins.
1.2 How to read this manual
This user manual describes parts LPC1311, LPC1313, LPC1342, LPC1343. Part-specific
features and registers are listed at the beginning of each chapter.
Remark: The LPC13xx series consists of the LPC1300 series (parts LPC1311/13/42/43)
and the LPC1300L series (parts LPC1311/01 and LPC1313/01). The LPC1300L series
features the following enhancements over the LPC1300 series:
• Power profiles with lower power consumption in Active and Sleep modes.
• Four levels for BOD forced reset.
• Second SSP controller (LPC1313FBD48/01 only).
• Windowed Watchdog Timer (WWDT).
• Internal pull-up resistors pull up pins to full V
DD
level.
• Programmable pseudo open-drain mode for GPIO pins.
1.3 Features
• ARM Cortex-M3 processor, running at frequencies of up to 72 MHz.
• ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
• 32 kB (LPC1343/13)/16 kB (LPC1342)/8 kB (LPC1311) on-chip flash programming
memory.
• 8 kB (LPC1343/13)/4 kB (LPC1342/11) SRAM.
• In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
• Selectable boot-up: UART or USB (USB on LPC134x only).
• On LPC134x: USB MSC and HID on-chip drivers.
• Serial interfaces:
UM10375
Chapter 1: LPC13xx Introductory information
Rev. 3 — 14 June 2011 User manual

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NXP Semiconductors LPC1311 Specifications

General IconGeneral
BrandNXP Semiconductors
ModelLPC1311
CategoryController
LanguageEnglish

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