UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 342 of 368
NXP Semiconductors
UM10375
Chapter 21: LPC13xx Flash memory programming firmware
21.15.2 Serial Wire Debug (SWD) flash programming interface
Debug tools can write parts of the flash image to RAM and then execute the IAP call
"Copy RAM to flash" repeatedly with proper offset.
21.16 Register description
21.16.1 Flash configuration register
Depending on the system clock frequency, access to the flash memory can be configured
with various access times by writing to the FLASHCFG register at address 0x4003 C010.
Remark: Improper setting of this register may result in incorrect operation of the LPC13xx
flash memory.
Table 345. Memory mapping in debug mode
Memory mapping mode Memory start address visible at 0x0000 0004
Bootloader mode 0x1FFF 0000
User flash mode 0x0000 0000
User SRAM mode 0x1000 0000
Table 346. Register overview: FMC (base address 0x4003 C000)
Name Access Address
offset
Description Reset
value
Reference
FLASHCFG R/W 0x010 Flash configuration register - Table 347
FMSSTART R/W 0x020 Signature start address register 0 Table 348
FMSSTOP R/W 0x024 Signature stop-address register 0 Table 349
FMSW0 R 0x02C Word 0 [31:0] - Table 350
FMSW1 R 0x030 Word 1 [63:32] - Table 351
FMSW2 R 0x034 Word 2 [95:64] - Table 352
FMSW3 R 0x038 Word 3 [127:96] - Table 353
FMSTAT R 0xFE0 Signature generation status register 0
Section 21.
16.4
FMSTATCLR W 0xFE8 Signature generation status clear
register
-
Section 21.
16.5
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