UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 16 of 368
NXP Semiconductors
UM10375
Chapter 3: LPC13xx System configuration
3.5.1 System memory remap register
The system memory remap register selects whether the ARM interrupt vectors are read
from the boot ROM, the flash, or the SRAM.
CLKOUTDIV R/W 0x0E8 CLKOUT clock divider 0x0000 0000 Table 39
- - 0x0EC - 0x0FC Reserved - -
PIOPORCAP0 R 0x100 POR captured PIO status 0 - Table 40
PIOPORCAP1 R 0x104 POR captured PIO status 1 - Table 40
- - 0x108 - 0x14C Reserved 0x0000 0000 -
BODCTRL R/W 0x150 BOD control 0x0000 0000 Table 42
SYSTCKCAL R/W 0x154 System tick counter calibration 0x0000 0004 Table 43
- - 0x158 - 0x1FC Reserved - -
STARTAPRP0 R/W 0x200 Start logic edge control register 0; bottom
32 interrupts
- Table 44
STARTERP0 R/W 0x204 Start logic signal enable register 0;
bottom 32 interrupts
- Table 45
STARTRSRP0CLR W 0x208 Start logic reset register 0; bottom 32
interrupts
- Table 46
STARTSRP0 R 0x20C Start logic status register 0; bottom 32
interrupts
- Table 47
STARTAPRP1 R/W 0x210 Start logic edge control register 1; top 8
interrupts
- Table 48
STARTERP1 R/W 0x214 Start logic signal enable register 1; top 8
interrupts
- Table 49
STARTRSRP1CLR W 0x218 Start logic reset register 1; top 8
interrupts
- Table 50
STARTSRP1 R 0x21C Start logic status register 1; top 8
interrupts
- Table 51
- - 0x220 - 0x22C Reserved - -
PDSLEEPCFG R/W 0x230 Power-down states in Deep-sleep mode 0x0000 0000 Table 53
PDAWAKECFG R/W 0x234 Power-down states after wake-up from
Deep-sleep mode
0x0000 FDF0 Table 54
PDRUNCFG R/W 0x238 Power-down configuration register 0x0000 FDF0 Table 55
- - 0x23C - 0x3F0 Reserved - -
DEVICE_ID R 0x3F4 Device ID part
dependent
Table 56
Table 7. Register overview: system control block (base address 0x4004 8000) …continued
Name Access Address offset Description Reset value Reference
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