UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 130 of 368
9.1 How to read this chapter
The number of GPIO pins available on each port depends on the LPC13xx part and the
package. See Table 146
for available GPIO pins:
9.2 Features
• GPIO pins can be configured as input or output by software.
• Each individual port pin can serve as an edge- or level-sensitive interrupt request.
• Interrupts can be configured on single falling or rising edges and on both edges.
• Level-sensitive interrupt pins can be HIGH- or LOW-active.
• All GPIO pins are inputs by default.
• Reading and writing of data registers are masked by address bits 13:2.
9.3 Pin description
[1] The pin configuration depends on the LPC13xx package (see Table 146).
UM10375
Chapter 9: LPC13xx General Purpose I/O (GPIO)
Rev. 3 — 14 June 2011 User manual
Table 146. GPIO configuration
Part Package GPIO port 0 GPIO port 1 GPIO port 2 GPIO port 3 Total
GPIO
pins
LPC1311,
LPC1311/01
HVQFN33 PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0 PIO3_2; PIO3_4;
PIO3_5
28
LPC1313,
LPC1313/01
LQFP48 PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0 to PIO2_11 PIO3_0 to PIO3_5 42
LPC1313 HVQFN33 PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0 PIO3_2; PIO3_4;
PIO3_5
28
LPC1342 LQFP48 PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0 to PIO2_11 PIO3_0 to PIO3_3 40
HVQFN33 PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0 PIO3_2 26
LPC1343 LQFP48 PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0 to PIO2_11 PIO3_0 to PIO3_3 40
HVQFN33 PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0 PIO3_2 26
Table 147. GPIO pin description
[1]
Pin Type Description
PIO0_0 to PIO0_11 I/O GPIO port 0 input/output pins.
PIO1_0 to PIO1_11 I/O GPIO port 1 input/output pins.
PIO2_0 to PIO2_11 I/O GPIO port 2 input/output pins.
PIO3_0 to PIO3_11 I/O GPIO port 3 input/output pins.
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