UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 83 of 368
NXP Semiconductors
UM10375
Chapter 6: LPC13xx Interrupt controller
6.6.23 Interrupt Priority Register 12
The IPR12 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 32 priorities, where 0 is the highest priority.
6.6.24 Interrupt Priority Register 13
The IPR13 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 32 priorities, where 0 is the highest priority.
Table 90. Interrupt Priority Register 12 (IPR12 - address 0xE000 E430) bit description
Bit Symbol Description
4:0 Unimplemented These bits ignore writes, and read as 0.
7:5 IP_USNFIQ USBFIQ Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest
priority.
12:8 Unimplemented These bits ignore writes, and read as 0.
15:13 IP_ADC ADC Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
20:16 Unimplemented These bits ignore writes, and read as 0.
23:21 IP_WDT WDT Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
28:24 Unimplemented These bits ignore writes, and read as 0.
31:29 IP_BOD BOD Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
Table 91. Interrupt Priority Register 13 (IPR13 - address 0xE000 E434) bit description
Bit Symbol Description
4:0 Unimplemented These bits ignore writes, and read as 0.
7:5 - Reserved.
12:8 Unimplemented These bits ignore writes, and read as 0.
15:13 IP_PIO3 PIO3 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
20:16 Unimplemented These bits ignore writes, and read as 0.
23:21 IP_PIO2 PIO2 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
28:24 Unimplemented These bits ignore writes, and read as 0.
31:29 IP_PIO1 PIO1 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
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