UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 209 of 368
NXP Semiconductors
UM10375
Chapter 13: LPC13xx I2C-bus controller
13.6 Pin description
The I
2
C-bus pins must be configured through the IOCON_PIO0_4 (Table 107) and
IOCON_PIO0_5 (Table 108
) registers for Standard/ Fast-mode or Fast-mode Plus. In
these modes, the I
2
C-bus pins are open-drain outputs and fully compatible with the
I
2
C-bus specification.
13.7 Clocking and power control
The clock to the I
2
C-bus interface (PCLK_I2C) is provided by the system clock (see
Figure 3
). This clock can be disabled through bit 5 in the SYSAHBCLKCTRL register
(Table 25
) for power savings.
Remark: Before accessing the I2C block, ensure that the I2C_RST_N bit (bit 1) in the
PRESETCTRL register (Table 9
) is set to 1. This de-asserts the reset signal to the I2C
block.
13.8 Register description
Table 215. I
2
C-bus pin description
Pin Type Description
SDA Input/Output I
2
C-bus Serial Data
SCL Input/Output I
2
C-bus Serial Clock
Table 216. Register overview: I
2
C (base address 0x4000 0000)
Name Access Address
offset
Description Reset
value
[1]
I2C0CONSET R/W 0x000 I2C Control Set Register. When a one is written to a bit of this register,
the corresponding bit in the I
2
C control register is set. Writing a zero has
no effect on the corresponding bit in the I
2
C control register.
0x00
I2C0STAT RO 0x004 I2C Status Register. During I
2
C operation, this register provides detailed
status codes that allow software to determine the next action needed.
0xF8
I2C0DAT R/W 0x008 I2C Data Register. During master or slave transmit mode, data to be
transmitted is written to this register. During master or slave receive
mode, data that has been received may be read from this register.
0x00
I2C0ADR0 R/W 0x00C I2C Slave Address Register 0. Contains the 7-bit slave address for
operation of the I
2
C interface in slave mode, and is not used in master
mode. The least significant bit determines whether a slave responds to
the General Call address.
0x00
I2C0SCLH R/W 0x010 SCH Duty Cycle Register High Half Word. Determines the high time of
the I
2
C clock.
0x04
I2C0SCLL R/W 0x014 SCL Duty Cycle Register Low Half Word. Determines the low time of
the I
2
C clock. I2nSCLL and I2nSCLH together determine the clock
frequency generated by an I
2
C master and certain times used in slave
mode.
0x04
I2C0CONCLR WO 0x018 I2C Control Clear Register. When a one is written to a bit of this register,
the corresponding bit in the I
2
C control register is cleared. Writing a zero
has no effect on the corresponding bit in the I
2
C control register.
NA
I2C0MMCTRL R/W 0x01C Monitor mode control register. 0x00
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