NXP Semiconductors LPC1311 User Manual

UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 72 of 368
NXP Semiconductors
UM10375
Chapter 6: LPC13xx Interrupt controller
6.6.7 Interrupt Clear-Pending Register 0 register
The ICPR0 register allows clearing the pending state of the first 32 peripheral interrupts,
or for reading the pending state of those interrupts. The remaining interrupts can have
their pending state cleared via the ICPR1 register (Section 6.6.8
). Setting the pending
state of interrupts is done through the ISPR0 and ISPR1 registers (Section 6.6.5
and
Section 6.6.6
).
The bit description is as follows for all bits in this register:
Write — Writing 0 has no effect, writing 1 changes the interrupt state to not pending.
Read — 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is
pending.
Table 73. Interrupt Set-Pending Register 1 register (ISPR1 - address 0xE000 E204) bit
description
Bit Symbol Description
0 ISP_PIO2_8 PIO0_0 start logic input interrupt pending set.
1 ISP_PIO2_9 PIO2_9 start logic input interrupt pending set.
2 ISP_PIO2_10 PIO2_10 start logic input interrupt pending set.
3 ISP_PIO2_11 PIO2_11 start logic input interrupt pending set.
4 ISP_PIO3_0 PIO3_0 start logic input interrupt pending set.
5 ISP_PIO3_1 PIO3_0 start logic input interrupt pending set.
6 ISP_PIO3_2 PIO3_0 start logic input interrupt pending set.
7 ISP_PIO3_3 PIO3_0 start logic input interrupt pending set.
8 ISP_I2C0 I
2
C0 interrupt pending set.
9 ISP_CT16B0 Timer CT16B0 interrupt pending set.
10 ISP_CT16B1 Timer CT16B1 interrupt pending set.
11 ISP_CT32B0 Timer CT32B0 interrupt pending set.
12 ISP_CT32B1 Timer CT32B1 interrupt pending set.
13 ISP_SSP0 SSP0 interrupt pending set.
14 ISP_UART UART interrupt pending set.
15 ISP_USBIRQ USB IRQ interrupt pending set.
16 ISP_USBFRQ USB FRQ interrupt pending set.
17 ISP_ADC ADC interrupt pending set.
18 ISP_WDT WDT interrupt pending set.
19 ISP_BOD BOD interrupt pending set.
20 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
21 ISP_PIO_3 GPIO port 3 interrupt pending set.
22 ISP_PIO_2 GPIO port 2 interrupt pending set.
23 ISP_PIO_1 GPIO port 1 interrupt pending set.
24 ISP_PIO_0 GPIO port 0 interrupt pending set.
25 ISP_SSP1 SSP1 interrupt pending set.
31:26 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NXP Semiconductors LPC1311 Specifications

General

Brand	NXP Semiconductors
Model	LPC1311
Category	Controller
Language	English