NXP Semiconductors LPC1311 User Manual

UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 38 of 368
NXP Semiconductors
UM10375
Chapter 3: LPC13xx System configuration
• BOD: Leaving the BOD circuit enabled will protect the part from a low voltage event
occurring while the part is in Deep-sleep mode. However, the BOD circuit causes an
additional current drain in Deep-sleep mode.
• WD oscillator: The watchdog oscillator can be left running in Deep-sleep mode to
provide a clock for the watchdog timer or a general purpose timer if they are needed
for timing a wake-up event (see Section 3.10.3
for details). In this case, the watchdog
oscillator analog output frequency must be set to its lowest value (bits FREQSEL in
the WDTOSCCTRL = 0001, see Table 15
) and all peripheral clocks other than the
timer clock must be disabled in the SYSAHBCLKCTRL register (see Table 25
) before
entering Deep-sleep mode.
The watchdog oscillator, if running, contributes an additional current drain in
Deep-sleep mode.
Remark: Reserved bits in this register must always be written as indicated. This register
must be initialized correctly before entering Deep-sleep mode.
3.5.46 Wake-up configuration register
The bits in this register can be programmed to determine the state the chip must enter
when it is waking up from Deep-sleep mode.
Remark: Reserved bits in this register must always be written as indicated. This register
must be initialized correctly before entering Deep-sleep mode.
Table 53. Deep-sleep configuration register (PDSLEEPCFG, address 0x4004 8230) bit
description
Bit Symbol Value Description Reset
value
2:0 FIXEDVAL - Reserved. Always write these bits as 111. 0
3 BOD_PD BOD power-down control in Deep-sleep mode, see
Table 52
.
0
0 Powered
1 Powered down
5:4 FIXEDVAL - Reserved. Always write these bits as 11. 0
6 WDTOSC_PD Watchdog oscillator power control in Deep-sleep
mode, see Table 52
.
0
0 Powered
1 Powered down
11:7 FIXEDVAL - Reserved. Always write these bits as 11111. 0
31:12 - 0 Reserved 0
Table 54. Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit
description
Bit Symbol Value Description Reset
value
0 IRCOUT_PD IRC oscillator output wake-up configuration 0
0 Powered
1 Powered down

NXP Semiconductors LPC1311 Specifications

General

Brand	NXP Semiconductors
Model	LPC1311
Category	Controller
Language	English