NXP Semiconductors LPC1311 User Manual

UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 299 of 368
18.1 How to read this chapter
This chapter describes the WDT block without the windowed watchdog features and
applies to the LPC1300 parts LPC1311/13/42/43.
18.2 Basic configuration
The WDT is configured using the following registers:
1. Pins: The WDT uses no external pins.
2. Power: In the SYSAHBCLKCTRL register, set bit 15 (Table 25
).
3. Peripheral clock: Select the WDT clock source (Table 34
) and enable the WDT
peripheral clock by writing to the WDTCLKDIV register (Table 36
).
Remark: The frequency of the watchdog oscillator is undefined after reset. The
watchdog oscillator frequency must be programmed by writing to the WDTOSCCTRL
register (see Table 15
) before using the watchdog oscillator for the WDT.
4. Lock features: Once the watchdog timer is enabled by setting the WDEN bit in the
WDMOD register, the WDEN bit cannot be disabled.
18.3 Features
• Internally resets chip if not periodically reloaded.
• Debug mode.
• Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to be
disabled.
• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
• Flag to indicate Watchdog reset.
• Programmable 24-bit timer with internal pre-scaler.
• Selectable time period from (T
WDCLK
 256  4) to (T
WDCLK
 2
24
 4) in multiples of
T
WDCLK
 4.
• The Watchdog clock (WDCLK) source is selected in the syscon block from the
Internal RC oscillator (IRC), the main clock, or the Watchdog oscillator, see Table 15
.
This gives a wide range of potential timing choices for Watchdog operation under
different power reduction conditions. For increased reliability, it also provides the
ability to run the Watchdog timer from an entirely internal source that is not dependent
on an external crystal and its associated components and wiring.
18.4 Applications
The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the Watchdog will generate a system
reset if the user program fails to "feed" (or reload) the Watchdog within a predetermined
amount of time.
UM10375
Chapter 18: LPC13xx WatchDog Timer (WDT)
Rev. 3 — 14 June 2011 User manual

NXP Semiconductors LPC1311 Specifications

General

Brand	NXP Semiconductors
Model	LPC1311
Category	Controller
Language	English