UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 82 of 368
NXP Semiconductors
UM10375
Chapter 6: LPC13xx Interrupt controller
6.6.21 Interrupt Priority Register 10
The IPR10 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 32 priorities, where 0 is the highest priority.
6.6.22 Interrupt Priority Register 11
The IPR11 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 32 priorities, where 0 is the highest priority.
Table 88. Interrupt Priority Register 10 (IPR10 - address 0xE000 E428) bit description
Bit Symbol Description
4:0 Unimplemented These bits ignore writes, and read as 0.
7:5 IP_I2C I2C Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
12:8 Unimplemented These bits ignore writes, and read as 0.
15:13 IP_CT16B0 CT16B0 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest
priority.
20:16 Unimplemented These bits ignore writes, and read as 0.
23:21 IP_CT16B1 CT16B1 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest
priority.
28:24 Unimplemented These bits ignore writes, and read as 0.
31:29 IP_CT32B0 CT32B0 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest
priority.
Table 89. Interrupt Priority Register 11 (IPR11 - address 0xE000 E42C) bit description
Bit Symbol Description
4:0 Unimplemented These bits ignore writes, and read as 0.
7:5 IP_CT32B1 CT32B1 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest
priority.
12:8 Unimplemented These bits ignore writes, and read as 0.
15:13 IP_SSP0 SSP0 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
20:16 Unimplemented These bits ignore writes, and read as 0.
23:21 IP_UART UART Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
28:24 Unimplemented These bits ignore writes, and read as 0.
31:29 IP_USBIRQ USBIRQ Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest
priority.
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