UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 18 of 368
NXP Semiconductors
UM10375
Chapter 3: LPC13xx System configuration
3.5.4 System PLL status register
This register is a Read-only register and supplies the PLL lock status (see Section 3.11.1).
3.5.5 USB PLL control register
The USB PLL is identical to the system PLL and is used to provide a dedicated clock to
the USB block if available (see Section 3.1
).
This register connects and enables the USB PLL and configures the PLL multiplier and
divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various
clock sources. The input frequency is multiplied up to a high frequency, then divided down
to provide the actual clock 48 MHz clock used by the USB subsystem.
Remark: The USB PLL must be connected to the system oscillator for correct USB
operation (see Table 20
).
Table 10. System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description
Bit Symbol Value Description Reset
value
4:0 MSEL Feedback divider value. The division value M is the
programmed MSEL value + 1.
00000: Division ratio M = 1
to
11111: Division ratio M = 32.
0x000
6:5 PSEL Post divider ratio P. The division ratio is 2 ï‚´ P. 0x00
0x0 P = 1
0x1 P = 2
0x2 P = 4
0x3 P = 8
31:7 - - Reserved. Do not write ones to reserved bits. 0x00
Table 11. System PLL status register (SYSPLLSTAT, address 0x4004 800C) bit description
Bit Symbol Value Description Reset
value
0 LOCK PLL lock status 0x0
0 PLL not locked
1 PLL locked
31:1 - - Reserved 0x00
Table 12. USB PLL control register (USBPLLCTRL, address 0x4004 8010) bit description
Bit Symbol Value Description Reset
value
4:0 MSEL Feedback divider value. The division value M is the
programmed MSEL value + 1.
00000: Division ratio M = 1
to
11111: Division ratio M = 32.
0x000
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