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User manual Rev. 3 — 14 June 2011 80 of 368
NXP Semiconductors
UM10375
Chapter 6: LPC13xx Interrupt controller
6.6.17 Interrupt Priority Register 6
The IPR6 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 32 priorities, where 0 is the highest priority.
6.6.18 Interrupt Priority Register 7
The IPR7 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 32 priorities, where 0 is the highest priority.
Table 84. Interrupt Priority Register 60 (IPR6 - address 0xE000 E418) bit description
Bit Symbol Description
4:0 Unimplemented These bits ignore writes, and read as 0.
7:5 IP_PIO2_0 PIO2_0 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
12:8 Unimplemented These bits ignore writes, and read as 0.
15:13 IP_PIO2_1 PIO2_1 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
20:16 Unimplemented These bits ignore writes, and read as 0.
23:21 IP_PIO2_2 PIO2_2 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
28:24 Unimplemented These bits ignore writes, and read as 0.
31:29 IP_PIO2_3 PIO2_3 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
Table 85. Interrupt Priority Register 7 (IPR7 - address 0xE000 E41C) bit description
Bit Symbol Description
4:0 Unimplemented These bits ignore writes, and read as 0.
7:5 IP_PIO2_4 PIO2_4 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
12:8 Unimplemented These bits ignore writes, and read as 0.
15:13 IP_PIO2_5 PIO2_5 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
20:16 Unimplemented These bits ignore writes, and read as 0.
23:21 IP_PIO2_6 PIO2_6 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
28:24 Unimplemented These bits ignore writes, and read as 0.
31:29 IP_PIO2_7 PIO2_7 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.