NXP Semiconductors LPC1311 User Manual

UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 34 of 368
NXP Semiconductors
UM10375
Chapter 3: LPC13xx System configuration
3.5.37 Start logic edge control register 0
The STARTAPRP0 register controls the start logic inputs of ports 0 (PIO0_0 to PIO0_11)
and 1 (PIO1_0 to PIO1_11) and the lower 8 inputs of port 2 (PIO2_0 to PIO2_7). This
register selects a falling or rising edge on the corresponding PIO input to produce a falling
or rising clock edge, respectively, for the start logic (see Section 3.10.2
).
Every bit in the STARTAPRP0 register controls one port input and is connected to one
wake-up interrupt in the NVIC. Bit 0 in the STARTAPRP0 register corresponds to interrupt
0, bit 1 to interrupt 1, etc. (see Table 66
). The bottom 32 interrupts are contained this
register, the top 8 interrupts are contained in the STARTAPRP1 register for total of 40
wake-up interrupts.
Remark: Each interrupt connected to a start logic input must be enabled in the NVIC if the
corresponding PIO pin is used to wake up the chip from Deep-sleep mode.
3.5.38 Start logic signal enable register 0
This STARTERP0 register enables or disables the start signal bits in the start logic. The bit
assignment is identical to Table 44
.
Table 44. Start logic edge control register 0 (STARTAPRP0, address 0x4004 8200) bit
description
Bit Symbol Description Reset
value
11:0 APRPIO0_n Edge select for start logic input PIO0_n (bit 0 = PIO0_0, ...,
bit 11 = PIO0_11).
0 = Falling edge.
1 = Rising edge.
0
23:12 APRPIO1_n Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ...,
bit 23 = PIO1_11).
0 = Falling edge.
1 = Rising edge.
0
31:24 APRPIO2_n Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ...,
bit 31 = PIO2_7).
0 = Falling edge.
1 = Rising edge.
0
Table 45. Start logic signal enable register 0 (STARTERP0, address 0x4004 8204) bit
description
Bit Symbol Description Reset
value
11:0 ERPIO0_n Enable start signal for start logic input PIO0_n (bit 0 = PIO0_0,
..., bit 11 = PIO0_11).
0 = Disabled.
1 = Enabled.
0
23:12 ERPIO1_n Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0,
..., bit 23 = PIO1_11).
0 = Disabled.
1 = Enabled.
0
31:24 ERPIO2_n Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0,
..., bit 31 = PIO2_7).
0 = Disabled.
1 = Enabled.
0

NXP Semiconductors LPC1311 Specifications

General

Brand	NXP Semiconductors
Model	LPC1311
Category	Controller
Language	English