NXP Semiconductors LPC1311 User Manual

UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 53 of 368
NXP Semiconductors
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Chapter 4: LPC13xx Power Management Unit (PMU)
4.2.2 General purpose registers 0 to 3
The general purpose registers retain data through the Deep power-down mode when
power is still applied to the V
DD
pin but the chip has entered Deep power-down mode.
Only a “cold” boot when all power has been completely removed from the chip will reset
the general purpose registers.
4.2.3 General purpose register 4
The general purpose register 4 retains data through the Deep power-down mode when
power is still applied to the V
DD
pin but the chip has entered Deep power-down mode.
Only a “cold” boot, when all power has been completely removed from the chip, will reset
the general purpose registers.
The hysteresis of the WAKEUP pin in Deep power-down mode can be controlled by bit 10
of this register.
Remark: If there is a possibility that the external voltage applied on pin V
DD
drops below
2.2 V during Deep power-down, the hysteresis of the WAKEUP input pin has to be
disabled in this register before entering Deep power-down mode in order for the chip to
wake up.
4.3 Functional description
See Section 3.9 for details on power management and the Deep power-down mode.
11 DPDFLAG Deep power-down flag 0x0
0 Read: Deep power-down mode not entered.
Write: No effect.
0x0
1 Read: Deep power-down mode entered.
Write: Clear the Deep power-down flag.
0x0
31:12 - - Reserved. Do not write ones to this bit. 0x0
Table 61. Power control register (PCON, address 0x4003 8000) bit description
…continued
Bit Symbol Value Description Reset
value
Table 62. General purpose registers 0 to 3 (GPREG0 - GPREG3, address 0x4003 8004 to
0x4003 8010) bit description
Bit Symbol Description Reset
value
31:0 GPDATA Data retained during Deep power-down mode. 0x0
Table 63. General purpose register 4 (GPREG4, address 0x4003 8014) bit description
Bit Symbol Value Description Reset
value
9:0 - - Reserved. Do not write ones to this bit. 0x0
10 WAKEUPHYS WAKEUP pin hysteresis enable 0x0
0 Hysteresis for WAKUP pin disabled.
1 Hysteresis for WAKEUP pin enabled.
31:11 GPDATA Data retained during Deep power-down mode. 0x0

NXP Semiconductors LPC1311 Specifications

General

Brand	NXP Semiconductors
Model	LPC1311
Category	Controller
Language	English