UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 62 of 368
6.1 How to read this chapter
Interrupts 47 and 48 in Table 66 are available on parts LPC1342/43 with USB only. These
interrupts are reserved on parts LPC1311/13.
Interrupt 57 is available for part LPC1313FBD48/01 only (48-pin package, LPC1300L
series). This interrupt is reserved on parts LPC1311/13/42/43 and LPC1311FHN33/01 and
LPC1313FHN33/01.
The implementation of start logic wake-up interrupts depends on how many PIO port pins
are available (see Section 3.1
). For HVQFN packages only wake-up interrupts 0 to 24 and
interrupt 38 are available.
6.2 Introduction
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M3. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
Refer to the Cortex-M3 Technical Reference Manual for details of NVIC operation.
6.3 Features
• Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M3.
• Tightly coupled interrupt controller provides low interrupt latency.
• Controls system exceptions and peripheral interrupts.
• In the LPC13xx, the NVIC supports up to 56 vectored interrupts.
• 8 programmable interrupt priority levels with hardware priority level masking.
• Relocatable vector table.
• Software interrupt generation.
6.4 Interrupt sources
Table 66 lists the interrupt sources for each peripheral function. Each peripheral device
may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may
represent more than one interrupt source. There is no significance or priority about what
line is connected where except for certain standards from ARM.
UM10375
Chapter 6: LPC13xx Interrupt controller
Rev. 3 — 14 June 2011 User manual
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