UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 51 of 368
NXP Semiconductors
UM10375
Chapter 3: LPC13xx System configuration
the Power-down mode is terminated by SYSPLL_PD (or USBPLL_PD) bits to zero in the
Power-down configuration register (Table 55
), the PLL will resume its normal operation
and will make the lock signal high once it has regained lock on the input clock.
3.12 Flash memory access
Depending on the system clock frequency, access to the flash memory can be configured
with various access times by writing to the FLASHCFG register at address 0x4003 C010.
This register is part of the flash controller block (see Figure 2
).
Remark: Improper setting of this register may result in incorrect operation of the LPC13xx
flash memory.
Table 59. Flash configuration register (FLASHCFG, address 0x4003 C010) bit description
Bit Symbol Value Description Reset
value
1:0 FLASHTIM Flash memory access time. FLASHTIM +1 is equal to the
number of system clocks used for flash access.
10
0x0 1 system clock flash access time (for system clock
frequencies of up to 20 MHz).
0x1 2 system clocks flash access time (for system clock
frequencies of up to 40 MHz).
0x2 3 system clocks flash access time (for system clock
frequencies of up to 72 MHz).
0x3 Reserved.
31:2 - - Reserved. User software must not change the value of
these bits. Bits 31:2 must be written back exactly as read.
-
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