NXP Semiconductors LPC1311 User Manual

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User manual Rev. 3 — 14 June 2011 212 of 368
NXP Semiconductors
UM10375
Chapter 13: LPC13xx I2C-bus controller
2. The General Call address has been received while the General Call bit (GC) in I2ADR
is set.
3. A data byte has been received while the I
2
C is in the master receiver mode.
4. A data byte has been received while the I
2
C is in the addressed slave receiver mode
The AA bit can be cleared by writing 1 to the AAC bit in the I2CONCLR register. When AA
is 0, a not acknowledge (HIGH level to SDA) will be returned during the acknowledge
clock pulse on the SCL line on the following situations:
1. A data byte has been received while the I
2
C is in the master receiver mode.
2. A data byte has been received while the I
2
C is in the addressed slave receiver mode.
13.8.2 I
2
C Status register (I2C0STAT - 0x4000 0004)
Each I
2
C Status register reflects the condition of the corresponding I
2
C interface. The I
2
C
Status register is Read-Only.
The three least significant bits are always 0. Taken as a byte, the status register contents
represent a status code. There are 26 possible status codes. When the status code is
0xF8, there is no relevant information available and the SI bit is not set. All other 25 status
codes correspond to defined I
2
C states. When any of these states entered, the SI bit will
be set. For a complete list of status codes, refer to tables from Table 235
to Table 238.
13.8.3 I
2
C Data register (I2C0DAT - 0x4000 0008)
This register contains the data to be transmitted or the data just received. The CPU can
read and write to this register only while it is not in the process of shifting a byte, when the
SI bit is set. Data in I2DAT remains stable as long as the SI bit is set. Data in I2DAT is
always shifted from right to left: the first bit to be transmitted is the MSB (bit 7), and after a
byte has been received, the first bit of received data is located at the MSB of I2DAT.
13.8.4 I
2
C Slave Address register 0 (I2C0ADR0- 0x4000 000C)
This register is readable and writable and are only used when an I
2
C interface is set to
slave mode. In master mode, this register has no effect. The LSB of I2ADR is the General
Call bit. When this bit is set, the General Call address (0x00) is recognized.
Table 218. I
2
C Status register (I2C0STAT - 0x4000 0004) bit description
Bit Symbol Description Reset value
2:0 - These bits are unused and are always 0. 0
7:3 Status These bits give the actual status information about the I
2
C
interface.
0x1F
31:8 - Reserved. The value read from a reserved bit is not defined. -
Table 219. I
2
C Data register (I2C0DAT - 0x4000 0008) bit description
Bit Symbol Description Reset value
7:0 Data This register holds data values that have been received or are to
be transmitted.
0
31:8 - Reserved. The value read from a reserved bit is not defined. -

NXP Semiconductors LPC1311 Specifications

General

Brand	NXP Semiconductors
Model	LPC1311
Category	Controller
Language	English