UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 24 of 368
NXP Semiconductors
UM10375
Chapter 3: LPC13xx System configuration
3.5.14 USB PLL clock source update enable register
This register updates the clock source of the USB PLL with the new input clock after the
USBPLLCLKSEL register has been written to. In order for the update to take effect at the
USB PLL input, first write a zero to the USBPLLUEN register and then write a one to
USBPLLUEN.
Remark: The system oscillator must be selected in the USBPLLCLKSEL register in order
to use the USB PLL, and this register must be toggled to update the USB PLL clock with
the system oscillator.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
3.5.15 Main clock source select register
This register selects the main system clock which can be either any input to the system
PLL, the output from the system PLL (sys_pllclkout), or the watchdog or IRC oscillators
directly. The main system clock clocks the core, the peripherals and memories, and
optionally the USB block.
The MAINCLKUEN register (see Section 3.5.16
) must be toggled from LOW to HIGH for
the update to take effect.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
3.5.16 Main clock source update enable register
This register updates the clock source of the main clock with the new input clock after the
MAINCLKSEL register has been written to. In order for the update to take effect, first write
a zero to the MAINCLKUEN register and then write a one to MAINCLKUEN.
Table 21. USB PLL clock source update enable register (USBPLLCLKUEN, address 0x4004
804C) bit description
Bit Symbol Value Description Reset value
0 ENA Enable USB PLL clock source update 0x0
0 No change
1 Update clock source
31:1 - - Reserved 0x00
Table 22. Main clock source select register (MAINCLKSEL, address 0x4004 8070) bit
description
Bit Symbol Value Description Reset value
1:0 SEL Clock source for main clock 0x00
0x0 IRC oscillator
0x1 Input clock to system PLL
0x2 WDT oscillator
0x3 System PLL clock out
31:2 - - Reserved 0x00