UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 40 of 368
NXP Semiconductors
UM10375
Chapter 3: LPC13xx System configuration
Remark: Reserved bits in this register must always be written as indicated. This register
must be initialized correctly before entering Deep-sleep mode.
[1] The system oscillator must be powered up and selected for the USB PLL to create a stable USB clock (see
Tab le 20
).
Table 55. Power-down configuration register (PDRUNCFG, address 0x4004 8238) bit
description
Bit Symbol Value Description Reset
value
0 IRCOUT_PD IRC oscillator output power-down 0
0 Powered
1 Powered down
1 IRC_PD IRC oscillator power-down 0
0 Powered
1 Powered down
2 FLASH_PD Flash power-down 0
0 Powered
1 Powered down
3 BOD_PD BOD power-down 0
0 Powered
1 Powered down
4 ADC_PD ADC power-down 1
0 Powered
1 Powered down
5 SYSOSC_PD System oscillator power-down
[1]
1
0 Powered
1 Powered down
6 WDTOSC_PD Watchdog oscillator power-down 1
0 Powered
1 Powered down
7 SYSPLL_PD System PLL power-down 1
0 Powered
1 Powered down
8 USBPLL_PD USB PLL power-down 1
0 Powered
1 Powered down
9 FIXEDVAL - Reserved. Always write this bit as 0. 0
10 USBPAD_PD USB pad power-down configuration 1
0 USB PHY powered
1 USB PHY powered down (suspend mode)
11 FIXEDVAL - Reserved. Always write this bit as 1. 1
31:12 - - Reserved 0
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