UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 84 of 368
NXP Semiconductors
UM10375
Chapter 6: LPC13xx Interrupt controller
6.6.25 Interrupt Priority Register 14
The IPR14 register controls the priority of four peripheral interrupts. Each interrupt can
have one of 32 priorities, where 0 is the highest priority.
6.6.26 Software Trigger Interrupt Register
The STIR register provides an alternate way for software to generate an interrupt, in
addition to using the ISPR registers. This mechanism can only be used to generate
peripheral interrupts, not system exceptions.
By default, only privileged software can write to the STIR register. Unprivileged software
can be given this ability if privileged software sets the USERSETMPEND bit in the ARM
Cortex-M3 CCR register.
Table 92. Interrupt Priority Register 14 (IPR14 - address 0xE000 E438) bit description
Bit Symbol Description
4:0 Unimplemented These bits ignore writes, and read as 0.
7:5 IP_PIO0 PIO0 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
12:8 Unimplemented These bits ignore writes, and read as 0.
15:13 IP_SSP1 SSP1 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
31:16 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Table 93. Software Trigger Interrupt Register (STIR - address 0xE000 EF00) bit description
Bit Symbol Description
8:0 INTID Writing a value to this field generates an interrupt for the specified the
interrupt number (see Table 66
). The range allowed for the LPC13xx is
0 to 57.
31:9 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
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