UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 286 of 368
NXP Semiconductors
UM10375
Chapter 16: LPC13xx 32-bit timer/counters (CT32B0/1)
16.8.7 Match Registers (TMR32B0MR0/1/2/3 - addresses 0x4001
4018/1C/20/24 and TMR32B1MR0/1/2/3 addresses 0x4001
8018/1C/20/24)
The Match register values are continuously compared to the Timer Counter value. When
the two values are equal, actions can be triggered automatically. The action possibilities
are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are
controlled by the settings in the MCR register.
5 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches
the TC.
0
1 Enabled
0 Disabled
6 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0
1 Enabled
0 Disabled
7 MR2R Reset on MR2: the TC will be reset if MR2 matches it. 0
1 Enabled
0 Disabled
8 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches
the TC.
0
1 Enabled
0 Disabled
9 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0
1 Enabled
0 Disabled
10 MR3R Reset on MR3: the TC will be reset if MR3 matches it. 0
1 Enabled
0 Disabled
11 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches
the TC.
0
1 Enabled
0 Disabled
31:12 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 276: Match Control Register (TMR32B0MCR - address 0x4001 4014 and TMR32B1MCR - address 0x4001 8014)
bit description
Bit Symbol Value Description Reset
value
Table 277: Match registers (TMR32B0MR0 to 3, addresses 0x4001 4018 to 24 and
TMR32B1MR0 to 3, addresses 0x4001 8018 to 24) bit description
Bit Symbol Description Reset
value
31:0 MATCH Timer counter match value. 0
To Next Page
Loading...
Need help?
General
