UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 63 of 368
NXP Semiconductors
UM10375
Chapter 6: LPC13xx Interrupt controller
[1] See Section 3.1 for wake-up pins not used in the HVQFN package.
Table 66. Connection of interrupt sources to the Vectored Interrupt Controller
Exception
Number
Vector
Offset
Function Flag(s)
39 to 0 start logic wake-up
interrupts
Each interrupt is connected to a PIO input pin serving
as wake-up pin from Deep-sleep mode (see
Section 3.5.37
and Section 3.5.41).
Interrupts 0 to 11 are connected to PIO0_0 to
PIO0_11; interrupts 12 to 23 are connected to
PIO1_0 to PIO1_11; interrupts 24 to 35 are
connected to PIO2_0 to PIO2_11; interrupts 36 to 39
are connected to PIO3_0 to PIO3_3.
[1]
40 0xA0 I2C0 SI (state change)
41 0xA4 CT16B0 Match 0 - 2
Capture 0
42 0xA8 CT16B1 Match 0 - 1
Capture 0
43 0xAC CT32B0 Match 0 - 3
Capture 0
44 0xB0 CT32B1 Match 0 - 3
Capture 0
45 0xB4 SSP0 Tx FIFO half empty
Rx FIFO half full
Rx Timeout
Rx Overrun
46 0xB8 UART Rx Line Status (RLS)
Transmit Holding Register Empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
Modem Control Change
End of Auto-Baud (ABEO)
Auto-Baud Time-Out (ABTO)
47 0xBC USB IRQ interrupt USB low-priority interrupt
48 0xC0 USB FIQ interrupt USB high-priority interrupt
49 0xC4 ADC A/D Converter end of conversion
50 0xC8 WDT Watchdog interrupt (WDINT)
51 0xCC BOD Brown-out detect
52 - - Reserved
53 0xD4 PIO_3 GPIO interrupt status of port 3
54 0xD8 PIO_2 GPIO interrupt status of port 2
55 0xDC PIO_1 GPIO interrupt status of port 1
56 0xE0 PIO_0 GPIO interrupt status of port 0
57 0xE4 SSP1 Tx FIFO half empty
Rx FIFO half full
Rx Timeout
Rx Overrun
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