NXP Semiconductors LPC1311 User Manual

UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 364 of 368
NXP Semiconductors
UM10375
Chapter 23: LPC13xx Supplementary information
12.5 Clocking and power control . . . . . . . . . . . . . 181
12.6 Register description . . . . . . . . . . . . . . . . . . . 181
12.6.1 UART Receiver Buffer Register (U0RBR -
0x4000 8000, when DLAB = 0, Read Only) . 183
12.6.2 UART Transmitter Holding Register (U0THR -
0x4000 8000 when DLAB = 0, Write Only). . 183
12.6.3 UART Divisor Latch LSB and MSB Registers
(U0DLL - 0x4000 8000 and U0DLM -
0x4000 8004, when DLAB = 1). . . . . . . . . . . 183
12.6.4 UART Interrupt Enable Register (U0IER -
0x4000 8004, when DLAB = 0). . . . . . . . . . . 184
12.6.5 UART Interrupt Identification Register (U0IIR -
0x4004 8008, Read Only). . . . . . . . . . . . . . . 185
12.6.6 UART FIFO Control Register (U0FCR -
0x4000 8008, Write Only). . . . . . . . . . . . . . . 187
12.6.7 UART Line Control Register (U0LCR -
0x4000 800C). . . . . . . . . . . . . . . . . . . . . . . . 188
12.6.8 UART Modem Control Register . . . . . . . . . . 189
12.6.8.1 Auto-flow control. . . . . . . . . . . . . . . . . . . . . . 190
12.6.8.1.1 Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
12.6.8.1.2 Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
12.6.9 UART Line Status Register (U0LSR -
0x4000 8014, Read Only). . . . . . . . . . . . . . . 192
12.6.10 UART Modem Status Register . . . . . . . . . . . 194
12.6.11 UART Scratch Pad Register (U0SCR -
0x4000 801C). . . . . . . . . . . . . . . . . . . . . . . . 194
12.6.12 UART Auto-baud Control Register (U0ACR -
0x4000 8020). . . . . . . . . . . . . . . . . . . . . . . . 195
12.6.13 Auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . . 195
12.6.14 Auto-baud modes. . . . . . . . . . . . . . . . . . . . . 196
12.6.15 UART Fractional Divider Register (U0FDR -
0x4000 8028). . . . . . . . . . . . . . . . . . . . . . . . 198
12.6.15.1 Baud rate calculation . . . . . . . . . . . . . . . . . . 199
12.6.15.1.1 Example 1: UART_PCLK = 14.7456 MHz, BR =
9600. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
12.6.15.1.2 Example 2: UART_PCLK = 12 MHz, BR =
115200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
12.6.16 UART Transmit Enable Register (U0TER -
0x4000 8030). . . . . . . . . . . . . . . . . . . . . . . . 201
12.6.17 UART RS485 Control register (U0RS485CTRL -
0x4000 804C) . . . . . . . . . . . . . . . . . . . . . . . 202
12.6.18 UART RS485 Address Match register
(U0RS485ADRMATCH - 0x4000 8050). . . . 203
12.6.19 UART1 RS485 Delay value register
(U0RS485DLY - 0x4000 8054) . . . . . . . . . . 203
12.6.20 RS-485/EIA-485 modes of operation. . . . . . 203
RS-485/EIA-485 Normal Multidrop Mode
(NMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
RS-485/EIA-485 Auto Address Detection (AAD)
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
RS-485/EIA-485 Auto Direction Control. . . . . 204
RS485/EIA-485 driver delay time. . . . . . . . . . 205
RS485/EIA-485 output inversion . . . . . . . . . . 205
12.7 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . 205
Chapter 13: LPC13xx I2C-bus controller
13.1 How to read this chapter. . . . . . . . . . . . . . . . 207
13.2 Basic configuration . . . . . . . . . . . . . . . . . . . . 207
13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
13.4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 207
13.5 General description. . . . . . . . . . . . . . . . . . . . 207
13.5.1 I
2
C Fast-mode Plus . . . . . . . . . . . . . . . . . . . 208
13.6 Pin description. . . . . . . . . . . . . . . . . . . . . . . . 209
13.7 Clocking and power control . . . . . . . . . . . . . 209
13.8 Register description . . . . . . . . . . . . . . . . . . . 209
13.8.1 I
2
C Control Set register (I2C0CONSET -
0x4000 0000) . . . . . . . . . . . . . . . . . . . . . . . . 210
13.8.2 I
2
C Status register (I2C0STAT - 0x4000 0004). . .
212
13.8.3 I
2
C Data register (I2C0DAT - 0x4000 0008) . 212
13.8.4 I
2
C Slave Address register 0 (I2C0ADR0-
0x4000 000C). . . . . . . . . . . . . . . . . . . . . . . . 212
13.8.5 I
2
C SCL HIGH and LOW duty cycle registers
(I2C0SCLH - 0x4000 0010 and I2C0SCLL-
0x4000 0014) . . . . . . . . . . . . . . . . . . . . . . . . 213
13.8.5.1 Selecting the appropriate I
2
C data rate and duty
cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
13.8.6 I
2
C Control Clear register (I2C0CONCLR -
0x4000 0018) . . . . . . . . . . . . . . . . . . . . . . . . 214
13.8.7 I
2
C Monitor mode control register (I2C0MMCTRL
- 0x4000 001C). . . . . . . . . . . . . . . . . . . . . . . 214
13.8.7.1 Interrupt in Monitor mode . . . . . . . . . . . . . . . 215
13.8.7.2 Loss of arbitration in Monitor mode . . . . . . . 216
13.8.8 I
2
C Slave Address registers (I2C0ADR[1, 2, 3]-
0x4000 00[20, 24, 28]). . . . . . . . . . . . . . . . . 216
13.8.9 I
2
C Data buffer register (I2C0DATA_BUFFER -
0x4000 002C) . . . . . . . . . . . . . . . . . . . . . . . 216
13.8.10 I
2
C Mask registers (I2C0MASK[0, 1, 2, 3] -
0x4000 00[30, 34, 38, 3C]) . . . . . . . . . . . . . 217
13.9 I
2
C operating modes. . . . . . . . . . . . . . . . . . . 217
13.9.1 Master Transmitter mode. . . . . . . . . . . . . . . 217
13.9.2 Master Receiver mode. . . . . . . . . . . . . . . . . 218
13.9.3 Slave Receiver mode. . . . . . . . . . . . . . . . . . 219
13.9.4 Slave Transmitter mode. . . . . . . . . . . . . . . . 220
13.10 I
2
C implementation and operation. . . . . . . . 220
13.10.1 Input filters and output stages . . . . . . . . . . . 221
13.10.2 Address Registers, I2ADDR0 to I2ADDR3 . 222
13.10.3 Address mask registers, I2MASK0 to
I2MASK3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
13.10.4 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . 222
13.10.5 Shift register, I2DAT . . . . . . . . . . . . . . . . . . . 222
13.10.6 Arbitration and synchronization logic . . . . . . 222
13.10.7 Serial clock generator . . . . . . . . . . . . . . . . . 223
13.10.8 Timing and control . . . . . . . . . . . . . . . . . . . . 224
13.10.9 Control register, I2CONSET and I2CONCLR 224
13.10.10 Status decoder and status register. . . . . . . . 224
13.11 Details of I
2
C operating modes . . . . . . . . . . 224
13.11.1 Master Transmitter mode. . . . . . . . . . . . . . . 225
13.11.2 Master Receiver mode. . . . . . . . . . . . . . . . . 229

NXP Semiconductors LPC1311 Specifications

General

Brand	NXP Semiconductors
Model	LPC1311
Category	Controller
Language	English