UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 121 of 368
NXP Semiconductors
UM10375
Chapter 8: LPC13xx Pin configuration
8.3 LPC131x pin configuration
(1) SSP1 or UART function on LPC1313FBD48/01 only.
Fig 12. LPC1313 LQFP48 package
LPC1313FBD48
LPC1313FBD48/01
PIO2_6 PIO3_0/DTR
(1)
PIO2_0/DTR/SSEL1
(1)
R/PIO1_2/AD3/CT32B1_MAT1
RESET/PIO0_0 R/PIO1_1/AD2/CT32B1_MAT0
PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO1_0/AD1/CT32B1_CAP0
V
SS
R/PIO0_11/AD0/CT32B0_MAT3
XTALIN PIO2_11/SCK0
XTALOUT PIO1_10/AD6/CT16B1_MAT1
V
DD
SWCLK/PIO0_10/SCK0/CT16B0_MAT2
PIO1_8/CT16B1_CAP0 PIO0_9/MOSI0/CT16B0_MAT1/SWO
PIO0_2/SSEL0/CT16B0_CAP0 PIO0_8/MISO0/CT16B0_MAT0
PIO2_7 PIO2_2/DCD/MISO1
(1)
PIO2_8 PIO2_10
PIO2_1/DSR/SCK1
(1)
PIO3_3/RI
(1)
PIO0_3 PIO1_7/TXD/CT32B0_MAT1
PIO0_4/SCL PIO1_6/RXD/CT32B0_MAT0
PIO0_5/SDA PIO1_5/RTS/CT32B0_CAP0
PIO1_9/CT16B1_MAT0 V
DD
PIO3_4 PIO3_2/DCD
(1)
PIO2_4 PIO1_11/AD7
PIO2_5 V
SS
PIO3_5 PIO1_4/AD5/CT32B1_MAT3/WAKEUP
PIO0_6/SCK0 SWDIO/PIO1_3/AD4/CT32B1_MAT2
PIO0_7/CTS
PIO2_9
PIO2_3/RI/MOSI1
(1)
PIO3_1/DSR
(1)
002aae513
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