UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 356 of 368
NXP Semiconductors
UM10375
Chapter 23: LPC13xx Supplementary information
Table 222. I
2
C SCL Low duty cycle register (I2C0SCLL -
0x4000 0014) bit description . . . . . . . . . . . . .213
Table 223. I2SCLL + I2SCLH values for selected I
2
C clock
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
Table 224. I
2
C Control Clear register (I2C0CONCLR -
0x4000 0018) bit description . . . . . . . . . . . . .214
Table 225. I
2
C Monitor mode control register (I2C0MMCTRL
- 0x4000 001C) bit description . . . . . . . . . . . .215
Table 226. I
2
C Slave Address registers (I2C0ADR[1, 2, 3]-
0x4000 00[20, 24, 28]) bit description . . . . . .216
Table 227. I
2
C Data buffer register (I2C0DATA_BUFFER -
0x4000 002C) bit description . . . . . . . . . . . . .217
Table 228. I
2
C Mask registers (I2C0MASK[0, 1, 2, 3] -
0x4000 00[30, 34, 38, 3C]) bit description . . .217
Table 229. I2C0CONSET and I2C1CONSET used to
configure Master mode. . . . . . . . . . . . . . . . . .218
Table 230. I2C0CONSET and I2C1CONSET used to
configure Slave mode. . . . . . . . . . . . . . . . . . .219
Table 231. Abbreviations used to describe an I
2
C
operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
Table 232. I2CONSET used to initialize Master Transmitter
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
Table 233. Master Transmitter mode. . . . . . . . . . . . . . . .227
Table 234. Master Receiver mode. . . . . . . . . . . . . . . . . .230
Table 235. I2C0ADR and I2C1ADR usage in Slave Receiver
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
Table 236. I2C0CONSET and I2C1CONSET used to
initialize Slave Receiver mode . . . . . . . . . . . .232
Table 237. Slave Receiver mode . . . . . . . . . . . . . . . . . .233
Table 238. Slave Transmitter mode. . . . . . . . . . . . . . . . .237
Table 239. Miscellaneous States. . . . . . . . . . . . . . . . . . .239
Table 240. SSP pin descriptions . . . . . . . . . . . . . . . . . . .251
Table 241. Register overview: SSP0 (base address 0x4004
0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252
Table 242. Register overview: SSP1 (base address 0x4005
8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252
Table 243: SSP Control Register 0 (SSP0CR0 - address
0x4004 0000, SSP1CR0 - address 0x4005 8000)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .254
Table 244: SSP Control Register 1 (SSP0CR1 - address
0x4004 0004, SSP1CR1 - address 0x4005 8004)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .255
Table 245: SSP Data Register (SSP0DR - address
0x4004 0008, SSP1DR - address 0x4005 8008)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .255
Table 246: SSP Status Register (SSP0SR - address
0x4004 000C, SSP1SR - address 0x4005 800C)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .256
Table 247: SSP Clock Prescale Register (SSP0CPSR -
address 0x4004 0010, SSP1CPSR - address
0x4005 8010) bit description . . . . . . . . . . . . .256
Table 248: SSP Interrupt Mask Set/Clear register
(SSP0IMSC - address 0x4004 0014, SSP1IMSC -
address 0x4005 8014) bit description. . . . . . .257
Table 249: Raw Interrupt Status register (SSP0RIS -
address 0x4004 0018, SSP1RIS - address
0x4005 8018) bit description . . . . . . . . . . . . .257
Table 250: SSP Masked Interrupt Status register (SSP0MIS
- address 0x4004 001C, SSP1MIS - address
0x4005 801C) bit description . . . . . . . . . . . . . 258
Table 251: SSP Interrupt Clear Register (SSP0ICR - address
0x4004 0020, SSP1ICR - address 0x4005 8020)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 258
Table 252. Counter/timer pin description . . . . . . . . . . . . 267
Table 253. Register overview: 16-bit counter/timer 0 CT16B0
(base address 0x4000 C000) . . . . . . . . . . . . 268
Table 254. Register overview: 16-bit counter/timer 1 CT16B1
(base address 0x4001 0000) . . . . . . . . . . . . 269
Table 255. Interrupt Register (TMR16B0IR - address
0x4000 C000 and TMR16B1IR - address
0x4001 0000) bit description . . . . . . . . . . . . . 270
Table 256. Timer Control Register (TMR16B0TCR - address
0x4000 C004 and TMR16B1TCR - address
0x4001 0004) bit description . . . . . . . . . . . . . 270
Table 257: Timer counter registers (TMR16B0TC, address
0x4000 C008 and TMR16B1TC 0x4001 0008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Table 258: Prescale registers (TMR16B0PR, address
0x4000 C00C and TMR16B1PR 0x4001 000C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Table 259: Prescale counter registers (TMR16B0PC,
address 0x4001 C010 and TMR16B1PC
0x4000 0010) bit description . . . . . . . . . . . . . 271
Table 260. Match Control Register (TMR16B0MCR -
address 0x4000 C014 and TMR16B1MCR -
address 0x4001 0014) bit description . . . . . 271
Table 261: Match registers (TMR16B0MR0 to 3, addresses
0x4000 C018 to 24 and TMR16B1MR0 to 3,
addresses 0x4001 0018 to 24) bit description 273
Table 262. Capture Control Register (TMR16B0CCR -
address 0x4000 C028 and TMR16B1CCR -
address 0x4001 0028) bit description . . . . . . 273
Table 263: Capture registers (TMR16B0CR0, address
0x4000 C02C and TMR16B1CR0, address
0x4001 002C) bit description . . . . . . . . . . . . . 273
Table 264. External Match Register (TMR16B0EMR -
address 0x4000 C03C and TMR16B1EMR -
address 0x4001 003C) bit description . . . . . . 274
Table 265. External match control . . . . . . . . . . . . . . . . . 275
Table 266. Count Control Register (TMR16B0CTCR -
address 0x4000 C070 and TMR16B1CTCR -
address 0x4001 0070) bit description . . . . . . 276
Table 267. PWM Control Register (TMR16B0PWMC -
address 0x4000 C074 and TMR16B1PWMC-
address 0x4001 0074) bit description . . . . . . 276
Table 268. Counter/timer pin description . . . . . . . . . . . . 281
Table 269. Register overview: 32-bit counter/timer 0 CT32B0
(base address 0x4001 4000) . . . . . . . . . . . . 282
Table 270. Register overview: 32-bit counter/timer 1 CT32B1
(base address 0x4001 8000) . . . . . . . . . . . . 283
Table 271: Interrupt Register (TMR32B0IR - address
0x4001 4000 and TMR32B1IR - address
0x4001 8000) bit description . . . . . . . . . . . . . 284
Table 272: Timer Control Register (TMR32B0TCR - address
0x4001 4004 and TMR32B1TCR - address
0x4001 8004) bit description . . . . . . . . . . . . . 284
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