UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
User manual Rev. 3 — 14 June 2011 2 of 368
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NXP Semiconductors
UM10375
LPC13xx User manual
Revision history
Rev Date Description
3 20110614 LPC1311/13/42/43 user manual
Modifications:
• Parts LPC1311/01 and LPC1313/01 added.
• Modifications to the user manual applicable to parts LPC1311/01 and LPC1313/01 only:
– SSP1 added for part LPC1313FBD48/01 in Chapter 3 “LPC13xx System
configuration” and Chapter 14 “LPC13xx SSP0/1”.
– UART functions for part LPC1313FBD48/01 added in Table 128, Table 129,
Table 134, and Table 138.
– Use of IRC for entering deep power-down updated in Section 3.9.4.2
.
– Enable sequence for UART clock updated in Section 12.1.
– Chapter 5 “LPC13xx Power profiles”
added.
– Register IOCON_DSR_LOC (Table 140
), IOCON_DCD_LOC (Table 141),
IOCON_RI_LOC (Table 142
) added.
– Programmable bit OD for pseudo open-drain mode added to IOCON registers in
Chapter 7
.
– Chapter 19 “LPC13xx Windowed WatchDog Timer (WWDT)” added.
• Editorial and formatting updates throughout the user manual.
• Pull-up level for internal pull-ups specified in Section 7.3.2 and Section 8.4.1 and
Section 8.4.2
.
• Description WDEN bit updated in Table 290 and Table 296 (WDMOD registers).
• Section 3.7 “Start-up behavior” added.
• NVIC priority register bit description updated in Section 6.6.
• Description of GPIO data register updated in Section 9.4.1.
• LPC1342FBD48 package added.
2 20100707 LPC1311/13/42/43 user manual
1 20091106 LPC1311/13/42/43 user manual
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