UM0306 Serial peripheral interface (SPI)
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16.4.3 SPI status register (SPI_SR)
Address Offset: 08h
Reset Value: 0000 0010 (0002h)
1514131211109876543210
Reserved BSY OVR MODF
CRC
ERR
Reserved TXE RXNE
r rcrcrc r r
Bits 15:8 Reserved. Forced to 0 by hardware.
Bit 7
BSY: Busy flag
0: SPI not busy
1: SPI is busy in communication or Tx buffer is not empty
This flag is set and reset by hardware.
Bit 6
OVR: Overrun flag
0: No Overrun occurred
1: Overrun occurred
This flag is set by hardware and reset by a software sequence. Refer to
Section 16.3.8 on page 368 for software sequence.
Bit 5
MODF: Mode fault
0: No Mode fault occurred
1: Mode fault occurred
This flag is set by hardware and reset by a software sequence. Refer to
Section 16.3.8 on page 368 for software sequence.
Bit 4
CRCERR: CRC error flag
0: CRC value received matches the SPI_RXCRCR value
1: CRC value received does not match the SPI_RXCRCR value
This flag is set by hardware and cleared by software writing 0.
Note:
This bit is only used in full-duplex mode.
Bit 3:2 Reserved. Forced to 0 by hardware.
Bit 1
TXE: Transmit buffer empty
0: Tx buffer not empty
1: Tx buffer empty
Bit 0
RXNE: Receive buffer not empty
0: Rx buffer empty
1: Rx buffer not empty
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